target/sh4: Enable disassembly via capstone
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson committed
Aug 8, 2026 at 12:47 UTC
2b386072864da25299991c4ca3d30efdd9466376
2 files changed
+21
include/disas/capstone.h
+7
@@ -71,4 +71,11 @@
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#define CS_MODE_RISCV_VENTANA 0
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#endif
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+#if CS_API_MAJOR < 5
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+#define CS_ARCH_SH -1
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+#define CS_MODE_SHFPU 0
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+#define CS_MODE_SH4 0
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+#define CS_MODE_SH4A 0
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+#endif
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+
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#endif /* QEMU_CAPSTONE_H */
target/sh4/cpu.c
+14
@@ -28,6 +28,7 @@
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#include "fpu/softfloat-helpers.h"
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#include "accel/tcg/cpu-ops.h"
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#include "tcg/tcg.h"
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+#include "disas/capstone.h"
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static void superh_cpu_set_pc(CPUState *cs, vaddr value)
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{
@@ -167,10 +168,23 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
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static void superh_cpu_disas_set_info(const CPUState *cpu,
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disassemble_info *info)
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{
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+ const CPUSH4State *env = cpu_env((CPUState *)cpu);
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+
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info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
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: BFD_ENDIAN_LITTLE;
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info->mach = bfd_mach_sh4;
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info->print_insn = print_insn_sh;
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+
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+ info->cap_arch = CS_ARCH_SH;
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+ info->cap_insn_unit = 2;
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+ info->cap_insn_split = 2;
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+ /*
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+ * Possible capstone bug: the isa levels are not additive:
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+ * least significant bit wins, so SH4 overrides SH4A.
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+ * Work around by setting one or the other but not both.
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+ */
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+ info->cap_mode = CS_MODE_SHFPU
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+ | (env->features & SH_FEATURE_SH4A ? CS_MODE_SH4A : CS_MODE_SH4);
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}
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static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)