target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207
PPC2_ALTIVEC_207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_ALTIVEC_207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-34-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Chinmay Rath committed
Aug 27, 2026 at 18:59 UTC
2b6c9a0ee983430eddf6e38eef90bf14f0a2482f
6 files changed
+64
-68
linux-user/ppc/elfload.c
+1
-2
@@ -116,8 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
116
do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
117
118
GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
119
- GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 |
120
- PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
119
+ GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
120
QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR));
121
GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
122
QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128);
target/ppc/cpu.h
+1
-3
@@ -2577,8 +2577,6 @@ enum {
2577
PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2578
/* ISA 2.06B floating point test instructions */
2579
PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2580
- /* ISA 2.07 Altivec */
2581
- PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2580
/* PowerISA 2.07 Book3s specification */
2581
PPC2_ISA207S = 0x0000000000008000ULL,
2582
/* Double precision floating point conversion for signed integer 64 */
@@ -2606,7 +2604,7 @@ enum {
2604
PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
2605
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2606
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2609
- PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2607
+ PPC2_ISA207S | PPC2_DFP | \
2608
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2609
PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
2610
PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \
target/ppc/cpu_init.c
+1
-1
@@ -6349,7 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
6349
pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
6350
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6351
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6352
- PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 |
6352
+ PPC2_FP_TST_ISA206 |
6353
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6354
PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6355
PPC2_BCDA_ISA206;
target/ppc/cpu_init.h
+1
-2
@@ -17,8 +17,7 @@
17
#define PPC_INSNS_FLAGS2_POWER_COMMON \
18
(PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \
19
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
20
- PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
21
- PPC2_ALTIVEC_207 | PPC2_ISA205 | \
20
+ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \
21
PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \
22
PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)
23
target/ppc/translate/vmx-impl.c.inc
+51
-51
@@ -351,14 +351,14 @@ static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX *a, MemOp vece,
351
TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add)
352
TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add)
353
TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add)
354
-TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add)
354
+TRANS_FLAGS2(ISA207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add)
355
356
TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub)
357
TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub)
358
TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub)
359
-TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub)
359
+TRANS_FLAGS2(ISA207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub)
360
361
-TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul)
361
+TRANS_FLAGS2(ISA207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul)
362
363
TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true)
364
TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true)
@@ -699,22 +699,22 @@ static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
699
TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv);
700
TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv);
701
TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv);
702
-TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
702
+TRANS_FLAGS2(ISA207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
703
704
TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv);
705
TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv);
706
TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv);
707
-TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
707
+TRANS_FLAGS2(ISA207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
708
709
TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv);
710
TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
711
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
712
-TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
712
+TRANS_FLAGS2(ISA207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
713
714
TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv)
715
TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv)
716
TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv)
717
-TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
717
+TRANS_FLAGS2(ISA207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
718
719
/* Logical operations */
720
TRANS_FLAGS(ALTIVEC, VAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_and);
@@ -722,30 +722,30 @@ TRANS_FLAGS(ALTIVEC, VANDC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_andc);
722
TRANS_FLAGS(ALTIVEC, VOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_or);
723
TRANS_FLAGS(ALTIVEC, VXOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_xor);
724
TRANS_FLAGS(ALTIVEC, VNOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nor);
725
-TRANS_FLAGS2(ALTIVEC_207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eqv);
726
-TRANS_FLAGS2(ALTIVEC_207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nand);
727
-TRANS_FLAGS2(ALTIVEC_207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_orc);
725
+TRANS_FLAGS2(ISA207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eqv);
726
+TRANS_FLAGS2(ISA207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nand);
727
+TRANS_FLAGS2(ISA207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_orc);
728
729
/* Integer Max/Min operations */
730
TRANS_FLAGS(ALTIVEC, VMAXUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umax);
731
TRANS_FLAGS(ALTIVEC, VMAXUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umax);
732
TRANS_FLAGS(ALTIVEC, VMAXUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umax);
733
-TRANS_FLAGS2(ALTIVEC_207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umax);
733
+TRANS_FLAGS2(ISA207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umax);
734
735
TRANS_FLAGS(ALTIVEC, VMAXSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smax);
736
TRANS_FLAGS(ALTIVEC, VMAXSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smax);
737
TRANS_FLAGS(ALTIVEC, VMAXSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smax);
738
-TRANS_FLAGS2(ALTIVEC_207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smax);
738
+TRANS_FLAGS2(ISA207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smax);
739
740
TRANS_FLAGS(ALTIVEC, VMINUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umin);
741
TRANS_FLAGS(ALTIVEC, VMINUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umin);
742
TRANS_FLAGS(ALTIVEC, VMINUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umin);
743
-TRANS_FLAGS2(ALTIVEC_207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umin);
743
+TRANS_FLAGS2(ISA207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umin);
744
745
TRANS_FLAGS(ALTIVEC, VMINSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smin);
746
TRANS_FLAGS(ALTIVEC, VMINSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smin);
747
TRANS_FLAGS(ALTIVEC, VMINSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smin);
748
-TRANS_FLAGS2(ALTIVEC_207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smin);
748
+TRANS_FLAGS2(ISA207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smin);
749
750
static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec vrb)
751
{
@@ -1091,16 +1091,16 @@ static bool do_vpk(DisasContext *ctx, arg_VX *a,
1091
1092
TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM)
1093
TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM)
1094
-TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM)
1094
+TRANS_FLAGS2(ISA207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM)
1095
TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS)
1096
TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS)
1097
-TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS)
1097
+TRANS_FLAGS2(ISA207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS)
1098
TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS)
1099
TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS)
1100
-TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS)
1100
+TRANS_FLAGS2(ISA207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS)
1101
TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS)
1102
TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS)
1103
-TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS)
1103
+TRANS_FLAGS2(ISA207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS)
1104
TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX)
1105
GEN_VXFORM_ENV(vsum4ubs, 4, 24);
1106
GEN_VXFORM_ENV(vsum4sbs, 4, 28);
@@ -1114,12 +1114,12 @@ GEN_VXFORM_ENV(vminfp, 5, 17);
1114
GEN_VXFORM_HETRO(vextublx, 6, 24)
1115
GEN_VXFORM_HETRO(vextuhlx, 6, 25)
1116
GEN_VXFORM_HETRO(vextuwlx, 6, 26)
1117
-GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
1117
+GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ISA207,
1118
vextuwlx, PPC_NONE, PPC2_ISA300)
1119
GEN_VXFORM_HETRO(vextubrx, 6, 28)
1120
GEN_VXFORM_HETRO(vextuhrx, 6, 29)
1121
GEN_VXFORM_HETRO(vextuwrx, 6, 30)
1122
-GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
1122
+GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ISA207,
1123
vextuwrx, PPC_NONE, PPC2_ISA300)
1124
1125
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
@@ -1209,16 +1209,16 @@ static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
1209
TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
1210
TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
1211
TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
1212
-TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1212
+TRANS_FLAGS2(ISA207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1213
1214
TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
1215
TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
1216
TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
1217
-TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1217
+TRANS_FLAGS2(ISA207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1218
TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
1219
TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
1220
TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
1221
-TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
1221
+TRANS_FLAGS2(ISA207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
1222
1223
TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
1224
TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
@@ -2330,11 +2330,11 @@ static bool do_va_helper(DisasContext *ctx, arg_VA *a,
2330
return true;
2331
}
2332
2333
-TRANS_FLAGS2(ALTIVEC_207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ)
2334
-TRANS_FLAGS2(ALTIVEC_207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM)
2333
+TRANS_FLAGS2(ISA207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ)
2334
+TRANS_FLAGS2(ISA207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM)
2335
2336
-TRANS_FLAGS2(ALTIVEC_207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM)
2337
-TRANS_FLAGS2(ALTIVEC_207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ)
2336
+TRANS_FLAGS2(ISA207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM)
2337
+TRANS_FLAGS2(ISA207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ)
2338
2339
TRANS_FLAGS(ALTIVEC, VPERM, do_va_helper, gen_helper_VPERM)
2340
TRANS_FLAGS2(ISA300, VPERMR, do_va_helper, gen_helper_VPERMR)
@@ -2502,14 +2502,14 @@ GEN_VXFORM_NOA(vpopcntb, 1, 28)
2502
GEN_VXFORM_NOA(vpopcnth, 1, 29)
2503
GEN_VXFORM_NOA(vpopcntw, 1, 30)
2504
GEN_VXFORM_NOA(vpopcntd, 1, 31)
2505
-GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
2506
- vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
2507
-GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
2508
- vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
2509
-GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
2510
- vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
2511
-GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
2512
- vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
2505
+GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ISA207, \
2506
+ vpopcntb, PPC_NONE, PPC2_ISA207)
2507
+GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ISA207, \
2508
+ vpopcnth, PPC_NONE, PPC2_ISA207)
2509
+GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ISA207, \
2510
+ vpopcntw, PPC_NONE, PPC2_ISA207)
2511
+GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ISA207, \
2512
+ vpopcntd, PPC_NONE, PPC2_ISA207)
2513
GEN_VXFORM(vbpermd, 6, 23);
2514
GEN_VXFORM(vbpermq, 6, 21);
2515
GEN_VXFORM_TRANS(vgbbd, 6, 20);
@@ -2589,8 +2589,8 @@ static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb_ps *a,
2589
return true;
2590
}
2591
2592
-TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD)
2593
-TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB)
2592
+TRANS_FLAGS2(ISA207, BCDADD, do_bcd_ps, gen_helper_BCDADD)
2593
+TRANS_FLAGS2(ISA207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB)
2594
TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS)
2595
TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS)
2596
TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN)
@@ -2622,10 +2622,10 @@ GEN_VXFORM(vcipherlast, 4, 20)
2622
GEN_VXFORM(vncipher, 4, 21)
2623
GEN_VXFORM(vncipherlast, 4, 21)
2624
2625
-GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
2626
- vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2627
-GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
2628
- vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2625
+GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ISA207,
2626
+ vcipherlast, PPC_NONE, PPC2_ISA207)
2627
+GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ISA207,
2628
+ vncipherlast, PPC_NONE, PPC2_ISA207)
2629
2630
#define VSHASIGMA(op) \
2631
static void gen_##op(DisasContext *ctx) \
@@ -2647,7 +2647,7 @@ VSHASIGMA(vshasigmad)
2647
2648
GEN_VXFORM3(vpermxor, 22, 0xFF)
2649
GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
2650
- vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
2650
+ vpermxor, PPC_NONE, PPC2_ISA207)
2651
2652
static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
2653
{
@@ -2815,13 +2815,13 @@ static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
2815
return true;
2816
}
2817
2818
-TRANS_FLAGS2(ALTIVEC_207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ)
2819
-TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper, gen_helper_VADDUQM)
2818
+TRANS_FLAGS2(ISA207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ)
2819
+TRANS_FLAGS2(ISA207, VADDUQM, do_vx_helper, gen_helper_VADDUQM)
2820
2821
-TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
2821
+TRANS_FLAGS2(ISA207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
2822
2823
-TRANS_FLAGS2(ALTIVEC_207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ)
2824
-TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
2823
+TRANS_FLAGS2(ISA207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ)
2824
+TRANS_FLAGS2(ISA207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
2825
2826
static void gen_VADDCUW_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
2827
{
@@ -3092,10 +3092,10 @@ TRANS_FLAGS(ALTIVEC, VMULESH, do_vx_helper, gen_helper_VMULESH)
3092
TRANS_FLAGS(ALTIVEC, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
3093
TRANS_FLAGS(ALTIVEC, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
3094
TRANS_FLAGS(ALTIVEC, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
3095
-TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
3096
-TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
3097
-TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
3098
-TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
3095
+TRANS_FLAGS2(ISA207, VMULESW, do_vx_helper, gen_helper_VMULESW)
3096
+TRANS_FLAGS2(ISA207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
3097
+TRANS_FLAGS2(ISA207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
3098
+TRANS_FLAGS2(ISA207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
3099
TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
3100
TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
3101
TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
target/ppc/translate/vmx-ops.c.inc
+9
-9
@@ -2,7 +2,7 @@
2
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
3
4
#define GEN_VXFORM_207(name, opc2, opc3) \
5
-GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
5
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA207)
6
7
#define GEN_VXFORM_300(name, opc2, opc3) \
8
GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
@@ -26,10 +26,10 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
26
27
GEN_VXFORM_300(vextublx, 6, 24),
28
GEN_VXFORM_300(vextuhlx, 6, 25),
29
-GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
29
+GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ISA207),
30
GEN_VXFORM_300(vextubrx, 6, 28),
31
GEN_VXFORM_300(vextuhrx, 6, 29),
32
-GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
32
+GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ISA207),
33
GEN_VXFORM_300(vsrv, 2, 28),
34
GEN_VXFORM_300(vslv, 2, 29),
35
GEN_VXFORM(vslo, 6, 16),
@@ -113,10 +113,10 @@ GEN_VXFORM_UIMM(vctsxs, 5, 15),
113
GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
114
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
115
116
-GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
117
-GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
118
-GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
119
-GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
116
+GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ISA207),
117
+GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ISA207),
118
+GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ISA207),
119
+GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ISA207),
120
121
GEN_VXFORM_300(vbpermd, 6, 23),
122
GEN_VXFORM_207(vbpermq, 6, 21),
@@ -127,8 +127,8 @@ GEN_VXFORM_207(vpmsumw, 4, 18),
127
128
GEN_VXFORM_207(vsbox, 4, 23),
129
130
-GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
131
-GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
130
+GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ISA207),
131
+GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ISA207),
132
133
GEN_VXFORM_207(vshasigmaw, 1, 26),
134
GEN_VXFORM_207(vshasigmad, 1, 27),