target/arm: Implement ID_AA64FPFR0
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
2bdfbfe7f803cc86429df7e261a25b47f9429b15
4 files changed
+22
-2
target/arm/cpu-features.h
+9
@@ -410,6 +410,15 @@ FIELD(ID_AA64SMFR0, I16I64, 52, 4)
410
FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
411
FIELD(ID_AA64SMFR0, FA64, 63, 1)
412
413
+FIELD(ID_AA64FPFR0, F8E5M2, 0, 1)
414
+FIELD(ID_AA64FPFR0, F8E4M3, 1, 1)
415
+FIELD(ID_AA64FPFR0, F8MM4, 26, 1)
416
+FIELD(ID_AA64FPFR0, F8MM8, 27, 1)
417
+FIELD(ID_AA64FPFR0, F8DP2, 28, 1)
418
+FIELD(ID_AA64FPFR0, F8DP4, 29, 1)
419
+FIELD(ID_AA64FPFR0, F8FMA, 30, 1)
420
+FIELD(ID_AA64FPFR0, F8CVT, 31, 1)
421
+
422
FIELD(ID_DFR0, COPDBG, 0, 4)
423
FIELD(ID_DFR0, COPSDBG, 4, 4)
424
FIELD(ID_DFR0, MMAPDBG, 8, 4)
target/arm/cpu-sysregs.h.inc
+1
@@ -3,6 +3,7 @@ DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
3
DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
4
DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)
5
DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
6
+DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7)
7
DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
8
DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
9
DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
target/arm/cpu.c
+1
@@ -1768,6 +1768,7 @@ static void arm_clear_aarch64_idregs(ARMCPU *cpu)
1768
SET_IDREG(&cpu->isar, ID_AA64AFR1, 0);
1769
SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0);
1770
SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0);
1771
+ SET_IDREG(&cpu->isar, ID_AA64FPFR0, 0);
1772
}
1773
1774
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
target/arm/helper.c
+11
-2
@@ -6477,11 +6477,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
6477
.access = PL1_R, .type = ARM_CP_CONST,
6478
.accessfn = access_tid3,
6479
.resetvalue = 0 },
6480
- { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
6480
+ { .name = "ID_AA64FPFR0_EL1", .state = ARM_CP_STATE_AA64,
6481
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
6482
.access = PL1_R, .type = ARM_CP_CONST,
6483
.accessfn = access_tid3,
6484
- .resetvalue = 0 },
6484
+ .resetvalue = GET_IDREG(isar, ID_AA64FPFR0) },
6485
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
6486
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
6487
.access = PL1_R, .type = ARM_CP_CONST,
@@ -6712,6 +6712,15 @@ void register_cp_regs_for_features(ARMCPU *cpu)
6712
R_ID_AA64SMFR0_I16I64_MASK |
6713
R_ID_AA64SMFR0_SMEVER_MASK |
6714
R_ID_AA64SMFR0_FA64_MASK },
6715
+ { .name = "ID_AA64FPFR0_EL1",
6716
+ .exported_bits = R_ID_AA64FPFR0_F8E5M2_MASK |
6717
+ R_ID_AA64FPFR0_F8E4M3_MASK |
6718
+ R_ID_AA64FPFR0_F8MM4_MASK |
6719
+ R_ID_AA64FPFR0_F8MM8_MASK |
6720
+ R_ID_AA64FPFR0_F8DP2_MASK |
6721
+ R_ID_AA64FPFR0_F8DP4_MASK |
6722
+ R_ID_AA64FPFR0_F8FMA_MASK |
6723
+ R_ID_AA64FPFR0_F8CVT_MASK },
6724
{ .name = "ID_AA64MMFR0_EL1",
6725
.exported_bits = R_ID_AA64MMFR0_ECV_MASK,
6726
.fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |