Merge tag 'pull-riscv-to-apply-20260824-1' of https://github.com/alistair23/qemu into staging

RISC-V PR for 11.1 * Fix IMSIC CSR write and add tests * Parametrise debug trigger number * Add 'svbare' satp-mode * Fix RINTC PLIC context ID for KVM * Avoid abort when reading vtype before env->xl is set * Skip reset for KVM irqchip * Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE * More FDT cleanups (PLIC) * Make FCTL.BE in IOMMU read only 0 * Check DC.TC reserved bits in IOMMU * Apply UXL WARL handling to vsstatus * Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU * Set RISCV_IOMMU_FQ_HDR_PV appropriately * Report QEMU CPU archid as 42 * Check PMP before updating PTE * Add the Tenstorrent Atlantis machine # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmqL2o0ACgkQr3yVEwxT # gBOC9g//Ux5snjOzJmmIgJdOFPcBlt1sRxq23Oc5uKoGp54yuDQFvhfg4t8G6w4L # pgJGdZ6MoA3D+QXsQuXS6WuVDKGuAwTcP4p4rioy+31WjFUL/2bTIOBFGkeER02x # uF2Z9fq8hF6bLjoOgyv2zyIL9hRY6Vh3cBCHaKXoLJdKmAdByhhHOOcvCpAfi17x # FmZ4pBZY7yApHIWNb3jBCR2siz8UZ2j0AvHbT2qMENHZBXW8GBrHDdMMOU5mexoB # nd+sKfiVyYpDJh0N99KzIJaxecK8rF/mt7FMghgKrf9sYMaHwundFl8O44skJ8+b # HDqAn8Cytfk659S1hiUJZF9Slt+zAAx1bKb7WWORP2hdfXkw5C5skyK0EGIEvb1R # 9FK+2Y0XI8dCoPXFOKaDOWOmTEW4ihAS1QZ/xZuhqOJK1jjQs7qik+8CNbhNVyqd # GHRZlenlGGtAE1CYELs3kOWVdxPyGQG4VVr9AXk/MmCQqcNtpG7E3gMcrg9a3LVg # vmIpAyc57MzvzEqGENIVoiSQRBtuF2T8EFnaLZv3PhXsHVGM+xz/BRGWTDza4TgC # hXS3xxk+UnSwRgjcx9kcMA+S74EjMML/1NmVHviD9dlC2yBGfYk0e90wDB+fJbn5 # XePzJX4moXSaLihTI+srqVmT5uvAoj6fGnmkS1XRwy1JdhWW7Tc= # =9pMS # -----END PGP SIGNATURE----- # gpg: Signature made Sun 23 Aug 2026 10:45:49 PM PDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260824-1' of https://github.com/alistair23/qemu: (96 commits) target/riscv/tcg: sret in virtual user mode raises virtual instruction exception target/riscv: Make Zcmt JVT loads endian-aware tests/tcg/riscv64: add misa write test riscv: csr: do not drop C bit on misa write target/riscv: Allow UXL to be 3 in mstatus on rv128 target/riscv: Fix sstatus update in rv128 target/riscv: Restore register dump zero padding tests/qtest: remove trace output from k230 watchdog test target/riscv: enforce even register constraints for Zdinx fcvt pairs target/riscv: reject FMV.X.W/FMV.W.X under Zfinx target/riscv: honor zicbo* envcfg gating in linux-user mode disas/riscv: Sort riscv-op.c.inc disas/riscv: Split rvi_opcode_data disas/riscv: Tidy decode of mop.r.n and mop.rr.n disas/riscv: Tidy decode of c.mop.n disas/riscv: Merge all c.mop.n to one pattern disas/riscv: Merge all mop.rr.n to one pattern disas/riscv: Merge all mop.r.n to one pattern disas/riscv: Split out riscv-op.c.inc disas/riscv: Move rv_op_illegal to riscv.c ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>