target/riscv: remove csr.h from kvm-cpu.c
Move riscv_new_csr_seed from csr.c to cpu.c since this function is shared with KVM. With that we can remove the csr.h from kvm-cpu.c. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703180538.3346781-10-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 3, 2026 at 15:05 UTC
2dc5b9d4efdb867f5f13402d149fa0045181c39f
5 files changed
+32
-34
target/riscv/cpu.c
+30
@@ -21,6 +21,7 @@
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#include "qemu/qemu-print.h"
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#include "qemu/ctype.h"
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#include "qemu/log.h"
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+#include "qemu/guest-random.h"
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#include "cpu.h"
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#include "cpu_vendorid.h"
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#include "target/riscv/csr.h"
@@ -556,6 +557,35 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
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}
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#endif
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+/* Used by csr.c and the KVM driver */
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+target_ulong riscv_new_csr_seed(target_ulong new_value,
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+ target_ulong write_mask)
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+{
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+ uint16_t random_v;
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+ Error *random_e = NULL;
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+ int random_r;
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+ target_ulong rval;
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+
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+ random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
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+ if (unlikely(random_r < 0)) {
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+ /*
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+ * Failed, for unknown reasons in the crypto subsystem.
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+ * The best we can do is log the reason and return a
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+ * failure indication to the guest. There is no reason
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+ * we know to expect the failure to be transitory, so
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+ * indicate DEAD to avoid having the guest spin on WAIT.
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+ */
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+ qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
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+ __func__, error_get_pretty(random_e));
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+ error_free(random_e);
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+ rval = SEED_OPST_DEAD;
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+ } else {
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+ rval = random_v | SEED_OPST_ES16;
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+ }
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+
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+ return rval;
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+}
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+
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static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
target/riscv/cpu.h
+2
-1
@@ -970,7 +970,8 @@ void riscv_add_satp_mode_properties(Object *obj);
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bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
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-
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+target_ulong riscv_new_csr_seed(target_ulong new_value,
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+ target_ulong write_mask);
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const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
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const char *priv_spec_to_str(int priv_version);
target/riscv/csr.h
-3
@@ -12,9 +12,6 @@
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#include "exec/target_long.h"
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#include "cpu_bits.h"
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-target_ulong riscv_new_csr_seed(target_ulong new_value,
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- target_ulong write_mask);
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-
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RISCVException riscv_csrr(CPURISCVState *env, int csrno,
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target_ulong *ret_value);
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target/riscv/kvm/kvm-cpu.c
-1
@@ -31,7 +31,6 @@
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#include "system/kvm.h"
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#include "system/kvm_int.h"
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#include "cpu.h"
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-#include "target/riscv/csr.h"
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#include "trace.h"
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#include "accel/accel-cpu-target.h"
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#include "hw/pci/pci.h"
target/riscv/tcg/csr.c
-29
@@ -29,7 +29,6 @@
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#include "exec/icount.h"
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#include "accel/tcg/cpu-loop.h"
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#include "accel/tcg/getpc.h"
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-#include "qemu/guest-random.h"
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#include "qapi/error.h"
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#include "tcg/insn-start-words.h"
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#include "internals.h"
@@ -5572,34 +5571,6 @@ static RISCVException write_mnstatus(CPURISCVState *env, int csrno,
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#endif
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/* Crypto Extension */
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-target_ulong riscv_new_csr_seed(target_ulong new_value,
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- target_ulong write_mask)
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-{
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- uint16_t random_v;
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- Error *random_e = NULL;
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- int random_r;
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- target_ulong rval;
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-
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- random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
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- if (unlikely(random_r < 0)) {
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- /*
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- * Failed, for unknown reasons in the crypto subsystem.
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- * The best we can do is log the reason and return a
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- * failure indication to the guest. There is no reason
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- * we know to expect the failure to be transitory, so
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- * indicate DEAD to avoid having the guest spin on WAIT.
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- */
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- qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
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- __func__, error_get_pretty(random_e));
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- error_free(random_e);
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- rval = SEED_OPST_DEAD;
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- } else {
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- rval = random_v | SEED_OPST_ES16;
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- }
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-
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- return rval;
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-}
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-
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static RISCVException rmw_seed(CPURISCVState *env, int csrno,
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target_ulong *ret_value,
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target_ulong new_value,