target/riscv: Fix size of guest_phys_fault_addr
Widen to 64 bits, and use hwaddr as argument to get_physical_address(). Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-7-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
2e05b6ec892880d9ff4fe5cc43e2b7368bccf081
3 files changed
+3
-4
target/riscv/cpu.h
+1
-1
@@ -238,7 +238,7 @@ struct CPUArchState {
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uint64_t badaddr;
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uint64_t bins;
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- target_ulong guest_phys_fault_addr;
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+ uint64_t guest_phys_fault_addr;
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target_ulong priv_ver;
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target_ulong vext_ver;
target/riscv/cpu_helper.c
+1
-2
@@ -1236,7 +1236,7 @@ static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
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*/
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static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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int *ret_prot, vaddr addr,
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- target_ulong *fault_pte_addr,
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+ hwaddr *fault_pte_addr,
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int access_type, int mmu_idx,
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bool first_stage, bool two_stage,
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bool is_debug, bool is_probe)
@@ -1876,7 +1876,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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ret = get_physical_address(env, &pa, &prot, address,
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&env->guest_phys_fault_addr, access_type,
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mmu_idx, true, true, false, probe);
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-
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/*
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* A G-stage exception may be triggered during two state lookup.
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* And the env->guest_phys_fault_addr has already been set in
target/riscv/machine.c
+1
-1
@@ -458,7 +458,7 @@ const VMStateDescription vmstate_riscv_cpu = {
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VMSTATE_UINT64(env.load_val, RISCVCPU),
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VMSTATE_UINT8(env.frm, RISCVCPU),
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VMSTATE_UINT64(env.badaddr, RISCVCPU),
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- VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
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+ VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU),
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VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
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VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
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VMSTATE_UINT32(env.misa_mxl, RISCVCPU),