target/arm/ptw: Restrict PMSAv8 code to TCG
Armv8-M Protected Memory System Architecture can only be emulated, therefore restrict it to TCG to avoid compiling it on hardware accelerators. Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260616153432.92939-3-philmd@oss.qualcomm.com>
Philippe Mathieu-Daudé committed
Jun 16, 2026 at 12:22 UTC
2ed7af82137176b81798ecd62799e9534e26b108
1 file changed
+19
-1
target/arm/ptw.c
+19
-1
@@ -13,11 +13,13 @@
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#include "exec/page-protection.h"
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#include "exec/target_page.h"
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#include "exec/tlb-flags.h"
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+#ifdef CONFIG_TCG
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#include "accel/tcg/probe.h"
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+#include "target/arm/tcg/idau.h"
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+#endif
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#include "cpu.h"
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#include "internals.h"
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#include "cpu-features.h"
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-#include "target/arm/tcg/idau.h"
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typedef struct S1Translate {
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/*
@@ -2818,6 +2820,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
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return (ptw->in_prot_check & ~result->f.prot) == 0;
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}
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+#ifdef CONFIG_TCG
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+
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static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint32_t secure)
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{
@@ -3247,6 +3251,20 @@ static bool get_phys_addr_pmsav8(CPUARMState *env,
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return ret;
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}
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+#else /* !CONFIG_TCG */
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+
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+static bool get_phys_addr_pmsav8(CPUARMState *env,
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+ S1Translate *ptw,
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+ uint32_t address,
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+ MMUAccessType access_type,
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+ GetPhysAddrResult *result,
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+ ARMMMUFaultInfo *fi)
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+{
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+ g_assert_not_reached();
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+}
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+
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+#endif /* !CONFIG_TCG */
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+
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/*
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* Translate from the 4-bit stage 2 representation of
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* memory attributes (without cache-allocation hints) to