95
#include "hw/cxl/cxl.h"
96
#include "hw/cxl/cxl_host.h"
97
#include "qemu/guest-random.h"
98
+#include "hw/watchdog/sbsa_gwdt.h"
99
100
static GlobalProperty arm_virt_compat_defaults[] = {
101
{ TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
215
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
216
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
217
[VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
218
+ [VIRT_GWDT_REFRESH] = { 0x0f000000, 0x00001000 },
219
+ [VIRT_GWDT_CONTROL] = { 0x0f001000, 0x00001000 },
220
[VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
221
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
222
[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
267
[VIRT_GPIO] = 7,
268
[VIRT_UART1] = 8,
269
[VIRT_ACPI_GED] = 9,
270
+ [VIRT_GWDT_WS0] = 10,
271
[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
272
[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
273
[VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
2089
create_smmuv3_dt_bindings(vms, base, size, irq);
2090
}
2091
2092
+static void create_gwdt_dt_bindings(VirtMachineState *vms)
2093
+{
2094
+ MachineState *ms = MACHINE(vms);
2095
+ hwaddr rbase = vms->memmap[VIRT_GWDT_REFRESH].base;
2096
+ hwaddr cbase = vms->memmap[VIRT_GWDT_CONTROL].base;
2097
+ int irq = vms->irqmap[VIRT_GWDT_WS0];
2098
+ char *nodename = g_strdup_printf("/watchdog@%" PRIx64, cbase);
2099
+
2100
+ qemu_fdt_add_subnode(ms->fdt, nodename);
2101
+ qemu_fdt_setprop_string(ms->fdt, nodename,
2102
+ "compatible", "arm,sbsa-gwdt");
2103
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
2104
+ 2, cbase, 2, SBSA_GWDT_CMMIO_SIZE,
2105
+ 2, rbase, 2, SBSA_GWDT_RMMIO_SIZE);
2106
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
2107
+ GIC_FDT_IRQ_TYPE_SPI, irq,
2108
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
2109
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "timeout-sec", 30);
2110
+ g_free(nodename);
2111
+}
2112
+
2113
static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
2114
{
2115
const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
3845
qlist_append_str(reserved_regions, resv_prop_str);
3846
qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
3847
g_free(resv_prop_str);
3848
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_WDT_SBSA)) {
3849
+ uint64_t cntfrq = object_property_get_int(OBJECT(qemu_get_cpu(0)),
3850
+ "cntfrq", &error_abort);
3851
+
3852
+ qdev_prop_set_uint64(dev, "clock-frequency", cntfrq);
3853
} else if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) {
3854
if (vms->legacy_smmuv3_present || vms->iommu == VIRT_IOMMU_VIRTIO) {
3855
error_setg(errp, "virt machine already has %s set. "
3901
{
3902
VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3903
3904
+ if (object_dynamic_cast(OBJECT(dev), TYPE_WDT_SBSA)) {
3905
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
3906
+ hwaddr rbase = vms->memmap[VIRT_GWDT_REFRESH].base;
3907
+ hwaddr cbase = vms->memmap[VIRT_GWDT_CONTROL].base;
3908
+ int irq = vms->irqmap[VIRT_GWDT_WS0];
3909
+
3910
+ sysbus_mmio_map(s, 0, rbase);
3911
+ sysbus_mmio_map(s, 1, cbase);
3912
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
3913
+
3914
+ create_gwdt_dt_bindings(vms);
3915
+ }
3916
+
3917
if (vms->platform_bus_dev) {
3918
MachineClass *mc = MACHINE_GET_CLASS(vms);
3919
4166
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
4167
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS);
4168
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ARM_SMMUV3);
4169
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_WDT_SBSA);
4170
#ifdef CONFIG_TPM
4171
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
4172
#endif