@samitouri / QOSamiQemu / commits / 302fec996c

tests/qtest/libqos: share Intel IOMMU test setup helpers

iommu-intel-test.c keeps the iommu-testdev PCI setup (save_fn(), setup_qtest_pci_device()) and the VT-d command-line / capability helpers (qvtd_iommu_args(), qvtd_check_caps()) as file-local statics. A second Intel IOMMU test would have to copy them, which defeats the purpose of the shared qos-intel-iommu module. Move them into qos-intel-iommu so sibling tests can reuse them: save_fn() becomes qvtd_save_pci_dev() and setup_qtest_pci_device() becomes qvtd_setup_qtest_pci_device(); qvtd_iommu_args() and qvtd_check_caps() keep their names. No functional change: iommu-intel-test now calls the public qvtd_setup_qtest_pci_device() instead of its file-local copy. Signed-off-by: Junjie Cao <junjie.cao@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20260703072200.463082-2-junjie.cao@intel.com>

Junjie Cao committed Jul 3, 2026 at 15:21 UTC 302fec996c31ac312278a6a756d66d053b80d2fa
3 files changed +101 -77
tests/qtest/iommu-intel-test.c
+1 -77
@@ -24,82 +24,6 @@ static uint64_t intel_iommu_expected_gpa(uint64_t iova)
24 return (QVTD_PT_VAL & VTD_PAGE_MASK_4K) + (iova & 0xfff);
25 }
26
27 -static void save_fn(QPCIDevice *dev, int devfn, void *data)
28 -{
29 - QPCIDevice **pdev = (QPCIDevice **) data;
30 -
31 - *pdev = dev;
32 -}
33 -
34 -static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibus,
35 - QPCIBar *bar)
36 -{
37 - QPCIDevice *dev = NULL;
38 -
39 - *pcibus = qpci_new_pc(qts, NULL);
40 - g_assert(*pcibus != NULL);
41 -
42 - qpci_device_foreach(*pcibus, IOMMU_TESTDEV_VENDOR_ID,
43 - IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev);
44 -
45 - g_assert(dev);
46 - qpci_device_enable(dev);
47 - *bar = qpci_iomap(dev, 0, NULL);
48 - g_assert_false(bar->is_io);
49 -
50 - return dev;
51 -}
52 -
53 -static const char *qvtd_iommu_args(QVTDTransMode mode)
54 -{
55 - switch (mode) {
56 - case QVTD_TM_SCALABLE_FLT:
57 - return "-device intel-iommu,scalable-mode=on,fsts=on ";
58 - case QVTD_TM_SCALABLE_PT:
59 - case QVTD_TM_SCALABLE_SLT:
60 - return "-device intel-iommu,scalable-mode=on ";
61 - default:
62 - return "-device intel-iommu ";
63 - }
64 -}
65 -
66 -static bool qvtd_check_caps(QTestState *qts, QVTDTransMode mode)
67 -{
68 - uint64_t ecap = qtest_readq(qts,
69 - Q35_HOST_BRIDGE_IOMMU_ADDR + DMAR_ECAP_REG);
70 -
71 - /* All scalable modes require SMTS */
72 - if (qvtd_is_scalable(mode) && !(ecap & VTD_ECAP_SMTS)) {
73 - g_test_skip("ECAP.SMTS not supported");
74 - return false;
75 - }
76 -
77 - switch (mode) {
78 - case QVTD_TM_SCALABLE_PT:
79 - if (!(ecap & VTD_ECAP_PT)) {
80 - g_test_skip("ECAP.PT not supported");
81 - return false;
82 - }
83 - break;
84 - case QVTD_TM_SCALABLE_SLT:
85 - if (!(ecap & VTD_ECAP_SSTS)) {
86 - g_test_skip("ECAP.SSTS not supported");
87 - return false;
88 - }
89 - break;
90 - case QVTD_TM_SCALABLE_FLT:
91 - if (!(ecap & VTD_ECAP_FSTS)) {
92 - g_test_skip("ECAP.FSTS not supported");
93 - return false;
94 - }
95 - break;
96 - default:
97 - break;
98 - }
99 -
100 - return true;
101 -}
102 -
27 static void run_intel_iommu_translation(const QVTDTestConfig *cfg)
28 {
29 QTestState *qts;
@@ -124,7 +48,7 @@ static void run_intel_iommu_translation(const QVTDTestConfig *cfg)
48 }
49
50 /* Setup and configure IOMMU-testdev PCI device */
127 - dev = setup_qtest_pci_device(qts, &pcibus, &bar);
51 + dev = qvtd_setup_qtest_pci_device(qts, &pcibus, &bar);
52 g_assert(dev);
53
54 g_test_message("### Intel IOMMU translation mode=%d ###", cfg->trans_mode);
tests/qtest/libqos/qos-intel-iommu.c
+77
@@ -11,6 +11,7 @@
11 #include "qemu/osdep.h"
12 #include "hw/i386/intel_iommu_internal.h"
13 #include "tests/qtest/libqos/pci.h"
14 +#include "tests/qtest/libqos/pci-pc.h"
15 #include "qos-iommu-testdev.h"
16 #include "qos-intel-iommu.h"
17
@@ -452,3 +453,79 @@ void qvtd_run_translation_case(QTestState *qts, QPCIDevice *dev,
453 }
454 }
455 }
456 +
457 +const char *qvtd_iommu_args(QVTDTransMode mode)
458 +{
459 + switch (mode) {
460 + case QVTD_TM_SCALABLE_FLT:
461 + return "-device intel-iommu,scalable-mode=on,fsts=on ";
462 + case QVTD_TM_SCALABLE_PT:
463 + case QVTD_TM_SCALABLE_SLT:
464 + return "-device intel-iommu,scalable-mode=on ";
465 + default:
466 + return "-device intel-iommu ";
467 + }
468 +}
469 +
470 +bool qvtd_check_caps(QTestState *qts, QVTDTransMode mode)
471 +{
472 + uint64_t ecap = qtest_readq(qts,
473 + Q35_HOST_BRIDGE_IOMMU_ADDR + DMAR_ECAP_REG);
474 +
475 + /* All scalable modes require SMTS */
476 + if (qvtd_is_scalable(mode) && !(ecap & VTD_ECAP_SMTS)) {
477 + g_test_skip("ECAP.SMTS not supported");
478 + return false;
479 + }
480 +
481 + switch (mode) {
482 + case QVTD_TM_SCALABLE_PT:
483 + if (!(ecap & VTD_ECAP_PT)) {
484 + g_test_skip("ECAP.PT not supported");
485 + return false;
486 + }
487 + break;
488 + case QVTD_TM_SCALABLE_SLT:
489 + if (!(ecap & VTD_ECAP_SSTS)) {
490 + g_test_skip("ECAP.SSTS not supported");
491 + return false;
492 + }
493 + break;
494 + case QVTD_TM_SCALABLE_FLT:
495 + if (!(ecap & VTD_ECAP_FSTS)) {
496 + g_test_skip("ECAP.FSTS not supported");
497 + return false;
498 + }
499 + break;
500 + default:
501 + break;
502 + }
503 +
504 + return true;
505 +}
506 +
507 +static void qvtd_save_pci_dev(QPCIDevice *dev, int devfn, void *data)
508 +{
509 + QPCIDevice **pdev = (QPCIDevice **)data;
510 +
511 + *pdev = dev;
512 +}
513 +
514 +QPCIDevice *qvtd_setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibus,
515 + QPCIBar *bar)
516 +{
517 + QPCIDevice *dev = NULL;
518 +
519 + *pcibus = qpci_new_pc(qts, NULL);
520 + g_assert(*pcibus != NULL);
521 +
522 + qpci_device_foreach(*pcibus, IOMMU_TESTDEV_VENDOR_ID,
523 + IOMMU_TESTDEV_DEVICE_ID, qvtd_save_pci_dev, &dev);
524 +
525 + g_assert(dev);
526 + qpci_device_enable(dev);
527 + *bar = qpci_iomap(dev, 0, NULL);
528 + g_assert_false(bar->is_io);
529 +
530 + return dev;
531 +}
tests/qtest/libqos/qos-intel-iommu.h
+23
@@ -182,4 +182,27 @@ void qvtd_run_translation_case(QTestState *qts, QPCIDevice *dev,
182 QPCIBar bar, uint64_t iommu_base,
183 const QVTDTestConfig *cfg);
184
185 +/*
186 + * qvtd_iommu_args - Build the -device intel-iommu command-line fragment
187 + * for the requested translation mode.
188 + */
189 +const char *qvtd_iommu_args(QVTDTransMode mode);
190 +
191 +/*
192 + * qvtd_check_caps - Check whether the running QEMU exposes the ECAP bits
193 + * required by @mode. Calls g_test_skip() and returns
194 + * false when a required capability is missing.
195 + */
196 +bool qvtd_check_caps(QTestState *qts, QVTDTransMode mode);
197 +
198 +/*
199 + * qvtd_setup_qtest_pci_device - Create a QPCIBus, locate the iommu-testdev
200 + * PCI function, enable it and map BAR0.
201 + *
202 + * On success, *pcibus and *bar are populated and the returned QPCIDevice
203 + * must be released by the caller via g_free().
204 + */
205 +QPCIDevice *qvtd_setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibus,
206 + QPCIBar *bar);
207 +
208 #endif /* QTEST_LIBQOS_INTEL_IOMMU_H */