@samitouri / QOSamiQemu / commits / 304df6d35e

target/mips: add Octeon COP2 crypto state

Add the common architectural state needed by Octeon's selector-driven COP2 crypto interfaces. This includes storage for the base hash, AES, CRC, GFM, 3DES, KASUMI, and overlapping HSH/SHA512/SHA3/SNOW3G/ZUC selector windows. Keep selector values and helper-local aliasing logic out of the CPU state header so the state definition remains limited to architectural storage. Helper code uses the same register banks instead of adding non-architectural shadow state. Model the SHA3 view as a direct 25-lane alias of the architectural HSH DAT/IV/SHA3_DAT24 storage. Migrate the state in an Octeon-only subsection so non-Octeon CPU models do not grow migration data. Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-1-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

James Hilliard committed Jun 8, 2026 at 12:59 UTC 304df6d35eb660883ac8a59968cce5cb2bddd060
2 files changed +53
target/mips/cpu.h
+26
@@ -537,6 +537,30 @@ struct TCState {
537 };
538
539 struct MIPSITUState;
540 +typedef struct MIPSOcteonCryptoState {
541 + union {
542 + struct {
543 + uint64_t hsh_dat[16];
544 + uint64_t hsh_iv[8];
545 + uint64_t sha3_dat24;
546 + };
547 + uint64_t sha3_dat[25];
548 + };
549 + uint64_t des3_key[3];
550 + uint64_t des3_iv;
551 + uint64_t des3_result;
552 + uint64_t aes_resinp[2];
553 + uint64_t aes_iv[2];
554 + uint64_t aes_key[4];
555 + uint32_t crc_poly;
556 + uint32_t crc_iv;
557 + uint64_t gfm_mul[2];
558 + uint64_t gfm_resinp[2];
559 + uint16_t gfm_poly;
560 + uint8_t aes_keylen;
561 + uint8_t crc_len;
562 +} MIPSOcteonCryptoState;
563 +
564 typedef struct CPUArchState {
565 TCState active_tc;
566 CPUMIPSFPUContext active_fpu;
@@ -558,6 +582,8 @@ typedef struct CPUArchState {
582 #define MSAIR_ProcID 8
583 #define MSAIR_Rev 0
584
585 + MIPSOcteonCryptoState octeon_crypto;
586 +
587 /*
588 * CP0 Register 0
589 */
target/mips/system/machine.c
+27
@@ -279,6 +279,32 @@ static const VMStateDescription mips_vmstate_octeon_multiplier = {
279 }
280 };
281
282 +static const VMStateDescription mips_vmstate_octeon_crypto = {
283 + .name = "cpu/octeon_crypto",
284 + .version_id = 1,
285 + .minimum_version_id = 1,
286 + .needed = mips_octeon_needed,
287 + .fields = (const VMStateField[]) {
288 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_dat, MIPSCPU, 16),
289 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_iv, MIPSCPU, 8),
290 + VMSTATE_UINT64(env.octeon_crypto.sha3_dat24, MIPSCPU),
291 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.des3_key, MIPSCPU, 3),
292 + VMSTATE_UINT64(env.octeon_crypto.des3_iv, MIPSCPU),
293 + VMSTATE_UINT64(env.octeon_crypto.des3_result, MIPSCPU),
294 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_resinp, MIPSCPU, 2),
295 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_iv, MIPSCPU, 2),
296 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_key, MIPSCPU, 4),
297 + VMSTATE_UINT32(env.octeon_crypto.crc_poly, MIPSCPU),
298 + VMSTATE_UINT32(env.octeon_crypto.crc_iv, MIPSCPU),
299 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_mul, MIPSCPU, 2),
300 + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_resinp, MIPSCPU, 2),
301 + VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU),
302 + VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU),
303 + VMSTATE_UINT8(env.octeon_crypto.crc_len, MIPSCPU),
304 + VMSTATE_END_OF_LIST()
305 + }
306 +};
307 +
308 const VMStateDescription vmstate_mips_cpu = {
309 .name = "cpu",
310 .version_id = 21,
@@ -396,6 +422,7 @@ const VMStateDescription vmstate_mips_cpu = {
422 .subsections = (const VMStateDescription * const []) {
423 &mips_vmstate_timer,
424 &mips_vmstate_octeon_multiplier,
425 + &mips_vmstate_octeon_crypto,
426 NULL
427 }
428 };