hw/riscv/atlantis: Integrate i2c controllers
Add DesignWare I2C controllers to the tt-atlantis machine. Provide a fixed clock in the device tree so that the Linux driver probes without WARNing. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-12-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Joel Stanley committed
Jun 30, 2026 at 12:19 UTC
30b505c4512287488f320e8f66eb17a10681aef1
3 files changed
+74
hw/riscv/Kconfig
+1
@@ -129,6 +129,7 @@ config TENSTORRENT
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select RISCV_IMSIC
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select SERIAL_MM
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select DEVICE_TREE
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+ select DESIGNWARE_I2C
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config XIANGSHAN_KUNMINGHU
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bool
hw/riscv/tt_atlantis.c
+59
@@ -54,6 +54,11 @@ static const MemMapEntry tt_atlantis_memmap[] = {
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[TT_ATL_ACLINT] = { 0xa2180000, 0x10000 },
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[TT_ATL_SIMSIC] = { 0xa4000000, 0x200000 },
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[TT_ATL_MAPLIC] = { 0xcc000000, 0x4000000 },
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+ [TT_ATL_I2C0] = { 0xd4040000, 0x10000 },
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+ [TT_ATL_I2C1] = { 0xd4050000, 0x10000 },
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+ [TT_ATL_I2C2] = { 0xd4060000, 0x10000 },
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+ [TT_ATL_I2C3] = { 0xd4070000, 0x10000 },
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+ [TT_ATL_I2C4] = { 0xd4080000, 0x10000 },
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[TT_ATL_UART1] = { 0xd4110000, 0x10000 },
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[TT_ATL_SAPLIC] = { 0xe8000000, 0x4000000 },
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[TT_ATL_DDR_HI] = { 0x100000000, 0x1000000000 },
@@ -275,10 +280,40 @@ static void create_fdt_rng(void *fdt)
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qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
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}
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+static void create_fdt_clk(void *fdt, const char *clock_name,
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+ uint32_t freq, uint32_t phandle)
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+{
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+ g_autofree char *name = g_strdup_printf("/clocks/%s", clock_name);
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+
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+ qemu_fdt_add_path(fdt, name);
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+ qemu_fdt_setprop_string(fdt, name, "compatible", "fixed-clock");
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+ qemu_fdt_setprop_string(fdt, name, "clock-output-names", clock_name);
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+ qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 0);
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+ qemu_fdt_setprop_cell(fdt, name, "clock-frequency", freq);
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+ qemu_fdt_setprop_cell(fdt, name, "phandle", phandle);
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+}
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+
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+static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq,
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+ uint32_t irqchip_phandle, uint32_t clk_phandle)
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+{
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+ g_autofree char *name = g_strdup_printf("/soc/i2c@%"HWADDR_PRIX, mem->base);
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+
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+ qemu_fdt_add_subnode(fdt, name);
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+ qemu_fdt_setprop_string(fdt, name, "compatible", "snps,designware-i2c");
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+ qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->size);
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+ qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle);
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+ qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4);
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+ qemu_fdt_setprop_cell(fdt, name, "clocks", clk_phandle);
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+ qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 100000);
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+ qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1);
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+ qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0);
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+}
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+
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static void finalize_fdt(TTAtlantisState *s)
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{
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uint32_t aplic_s_phandle = next_phandle();
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uint32_t imsic_s_phandle = next_phandle();
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+ uint32_t periph_clk_phandle = next_phandle();
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void *fdt = MACHINE(s)->fdt;
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create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle);
@@ -292,6 +327,15 @@ static void finalize_fdt(TTAtlantisState *s)
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create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1], TT_ATL_UART1_IRQ,
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aplic_s_phandle);
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+
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+ create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle);
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+
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+ for (int i = 0; i < TT_ATL_NUM_I2C; i++) {
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+ create_fdt_i2c(fdt,
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+ &s->memmap[TT_ATL_I2C0 + i],
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+ TT_ATL_I2C0_IRQ + i,
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+ aplic_s_phandle, periph_clk_phandle);
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+ }
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}
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static void create_fdt(TTAtlantisState *s)
@@ -492,6 +536,21 @@ static void tt_atlantis_machine_init(MachineState *machine)
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s->memmap[TT_ATL_UART1].base,
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s->memmap[TT_ATL_UART1].size);
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+ /* I2C */
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+ for (int i = 0; i < TT_ATL_NUM_I2C; i++) {
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+ SysBusDevice *sbd;
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+
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+ object_initialize_child(OBJECT(s), "i2c[*]", &s->i2c[i],
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+ TYPE_DESIGNWARE_I2C);
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+ sbd = SYS_BUS_DEVICE(&s->i2c[i]);
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+ sysbus_realize(sbd, &error_fatal);
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+ memory_region_add_subregion(system_memory,
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+ s->memmap[TT_ATL_I2C0 + i].base,
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+ sysbus_mmio_get_region(sbd, 0));
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+ sysbus_connect_irq(sbd, 0,
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+ qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + i));
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+ }
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+
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/* Load or create device tree */
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if (machine->dtb) {
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load_fdt(s);
include/hw/riscv/tt_atlantis.h
+14
@@ -11,12 +11,15 @@
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#include "hw/core/boards.h"
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#include "hw/core/sysbus.h"
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+#include "hw/i2c/designware_i2c.h"
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#include "hw/intc/riscv_imsic.h"
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#include "hw/riscv/riscv_hart.h"
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#define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis")
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OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE)
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+#define TT_ATL_NUM_I2C 5
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+
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struct TTAtlantisState {
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/*< private >*/
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MachineState parent;
@@ -27,11 +30,17 @@ struct TTAtlantisState {
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RISCVHartArrayState soc;
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DeviceState *irqchip;
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+ DesignWareI2CState i2c[TT_ATL_NUM_I2C];
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int fdt_size;
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};
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enum {
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+ TT_ATL_I2C0_IRQ = 33,
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+ TT_ATL_I2C1_IRQ = 34,
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+ TT_ATL_I2C2_IRQ = 35,
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+ TT_ATL_I2C3_IRQ = 36,
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+ TT_ATL_I2C4_IRQ = 37,
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TT_ATL_UART1_IRQ = 39,
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};
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@@ -40,6 +49,11 @@ enum {
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TT_ATL_BOOTROM,
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TT_ATL_DDR_LO,
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TT_ATL_DDR_HI,
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+ TT_ATL_I2C0,
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+ TT_ATL_I2C1,
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+ TT_ATL_I2C2,
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+ TT_ATL_I2C3,
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+ TT_ATL_I2C4,
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TT_ATL_MAPLIC,
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TT_ATL_MIMSIC,
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TT_ATL_SAPLIC,