@samitouri / QOSamiQemu / commits / 312f3ef8ad

intel_iommu: Rename pasid property to "pasid-bits" and define it as type uint8

'x-pasid-mode' is a bool property, we need an extra 'pss' property to represent PASID size supported. Because there is no any device in QEMU supporting pasid capability yet, no guest could use the pasid feature until now, 'x-pasid-mode' takes no effect. So instead of an extra 'pss' property we can use a single property of uint8 type and named 'pasid-bits' to represent if pasid is supported and the PASID bits size. A value of N > 0 means pasid is supported and N - 1 is the value in PSS field in ECAP register. PASID bits size should also be no more than 20 bits according to PCI spec. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Tested-by: Xudong Hao <xudong.hao@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260527054658.1021096-6-zhenzhong.duan@intel.com>

Zhenzhong Duan committed May 27, 2026 at 01:46 UTC 312f3ef8adcf008d3992012bcdc91ce26b6d9186

3 files changed +11 -4

hw/i386/intel_iommu.c

+9 -2

@@ -4203,7 +4203,7 @@ static const Property vtd_properties[] = {

4203 DEFINE_PROP_BOOL("scalable-mode", IntelIOMMUState, scalable_mode, FALSE),

4204 DEFINE_PROP_BOOL("fsts", IntelIOMMUState, fsts, FALSE),

4205 DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),

4206 - DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),

4206 + DEFINE_PROP_UINT8("pasid-bits", IntelIOMMUState, pasid, 0),

4207 DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, false),

4208 DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false),

4209 DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true),

@@ -5045,7 +5045,8 @@ static void vtd_cap_init(IntelIOMMUState *s)

5045 }

5046

5047 if (s->pasid) {

5048 - s->ecap |= VTD_ECAP_PASID | VTD_ECAP_PSS;

5048 + VTD_ECAP_SET_PSS(s, s->pasid - 1);

5049 + s->ecap |= VTD_ECAP_PASID;

5050 }

5051 }

5052

@@ -5586,6 +5587,12 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)

5587 return false;

5588 }

5589

5590 + if (s->pasid > PCI_EXT_CAP_PASID_MAX_WIDTH) {

5591 + error_setg(errp, "PASID width %d exceeds Max PASID Width %d allowed "

5592 + "in PCI spec", s->pasid, PCI_EXT_CAP_PASID_MAX_WIDTH);

5593 + return false;

5594 + }

5595 +

5596 if (s->svm) {

5597 if (!x86_iommu->dt_supported) {

5598 error_setg(errp, "Need to set device IOTLB for svm");

hw/i386/intel_iommu_internal.h

+1 -1

@@ -195,7 +195,7 @@

195 #define VTD_ECAP_MHMV (15ULL << 20)

196 #define VTD_ECAP_SRS (1ULL << 31)

197 #define VTD_ECAP_NWFS (1ULL << 33)

198 -#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid */

198 +#define VTD_ECAP_SET_PSS(x, v) ((x)->ecap = deposit64((x)->ecap, 35, 5, v))

199 #define VTD_ECAP_PASID (1ULL << 40)

200 #define VTD_ECAP_PDS (1ULL << 42)

201 #define VTD_ECAP_SMTS (1ULL << 43)

include/hw/i386/intel_iommu.h

+1 -1

@@ -314,7 +314,7 @@ struct IntelIOMMUState {

314 bool intr_eime; /* Extended interrupt mode enabled */

315 OnOffAuto intr_eim; /* Toggle for EIM cabability */

316 uint8_t aw_bits; /* Host/IOVA address width (in bits) */

317 - bool pasid; /* Whether to support PASID */

317 + uint8_t pasid; /* PASID supported in bits, 0 if not */

318 bool fs1gp; /* First Stage 1-GByte Page Support */

319

320 /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */