docs: simplify DiamondRapids CPU docs
This aligns the first line of the docs with the style used for previous CPU models, and simplifies the text in the remaining docs. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Daniel P. Berrangé committed
Feb 11, 2026 at 17:55 UTC
3275771e914fecfb89c5ee02f15034281b9afcfd
1 file changed
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docs/system/cpu-models-x86.rst.inc
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@@ -72,17 +72,13 @@ compatibility is required, use the newest CPU model that is compatible
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across all desired hosts.
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``DiamondRapids``
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- Intel Xeon Processor.
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+ Intel Xeon Processor (DiamondRapids, 2026)
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- Diamond Rapids product has a topology which differs from previous Xeon
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- products. It does not support SMT, but instead features a dual core
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- module (DCM) architecture. It also has core building blocks (CBB - die
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- level in CPU topology). The cache hierarchy is organized as follows:
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- L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per
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- CBB. This cache topology can be emulated for DiamondRapids CPU model
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- using the smp-cache configuration as shown below:
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-
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- Example:
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+ This does not include SMT but allows the module (dual core module
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+ - DCM) and die (core building block - CBB) topology levels. The
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+ cache hierarchy is L1 i/d cache per thread, L2 cache per module,
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+ and L3 cache per die, which can be emulated using the smp-cache
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+ option:
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::
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