target/arm: Enable FEAT_SME_LUTv2 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
332ec0f79b8285e06b7e588b7619367ba4c4195d
3 files changed
+3
docs/system/arm/emulation.rst
+1
@@ -165,6 +165,7 @@ the following architecture extensions:
165
- FEAT_SME_F16F16 (Non-widening half-precision FP16 arithmetic for SME2)
166
- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
167
- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
168
+- FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements)
169
- FEAT_SVE (Scalable Vector Extension)
170
- FEAT_SVE_AES (Scalable Vector AES instructions)
171
- FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2)
linux-user/aarch64/elfload.c
+1
@@ -222,6 +222,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
222
GET_FEATURE_ID(aa64_faminmax, ARM_HWCAP2_A64_FAMINMAX);
223
GET_FEATURE_ID(aa64_fpmr, ARM_HWCAP2_A64_FPMR);
224
GET_FEATURE_ID(aa64_lut, ARM_HWCAP2_A64_LUT);
225
+ GET_FEATURE_ID(aa64_sme2p1_lutv2, ARM_HWCAP2_A64_SME_LUTV2);
226
GET_FEATURE_ID(aa64_f8cvt, ARM_HWCAP2_A64_F8CVT |
227
ARM_HWCAP2_A64_F8E4M3 |
228
ARM_HWCAP2_A64_F8E5M2);
target/arm/tcg/cpu64.c
+1
@@ -1394,6 +1394,7 @@ void aarch64_max_tcg_initfn(Object *obj)
1394
t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
1395
t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
1396
t = FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* FEAT_SME2p1 */
1397
+ t = FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* FEAT_SME_LUTv2 */
1398
t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
1399
SET_IDREG(isar, ID_AA64SMFR0, t);
1400