hw/riscv: sifive_u: Align ROM reset vector data
The SiFive U ROM reset vector data needs proper 8-byte alignment for RV64 ld instructions. The misaligned load will cause exception when Zicclsm is supported as SiFive U CPU doesn't support hardware misaligned loads and stores. Add padding to ensure start_addr and fdt_load_addr are placed at 8-byte aligned offsets and adjust the load instruction offsets to match the new data layout. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260810055618.1175500-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Aug 10, 2026 at 13:56 UTC
340a8c111dbf1f8f5524c6cbe959dad9b9af56b1
1 file changed
+6
-5
hw/riscv/sifive_u.c
+6
-5
@@ -564,19 +564,20 @@ static void sifive_u_machine_init(MachineState *machine)
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0,
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0,
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0x00028067, /* jr t0 */
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+ 0x00000000, /* padding for alignment */
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start_addr, /* start: .dword */
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start_addr_hi32,
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fdt_load_addr, /* fdt_laddr: .dword */
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fdt_load_addr_hi32,
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- 0x00000000,
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/* fw_dyn: */
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};
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+
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if (riscv_is_32bit(&s->soc.u_cpus)) {
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- reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
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- reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
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+ reset_vec[4] = 0x0242a583; /* lw a1, 36(t0) */
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+ reset_vec[5] = 0x01c2a283; /* lw t0, 28(t0) */
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} else {
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- reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
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- reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
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+ reset_vec[4] = 0x0242b583; /* ld a1, 36(t0) */
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+ reset_vec[5] = 0x01c2b283; /* ld t0, 28(t0) */
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}
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