target/riscv: Fix size of priv_ver and vext_ver
Fix these fields to 32 bits, also update corresponding priv_ver field in DisasContext as well as function arguments. 32 bits was chosen since it's large enough to fit all stored values and int/int32_t is used in RISCVCPUDef and a few functions. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-8-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
3563de9ac777955477a6d7cc9c62ee5de73ef657
3 files changed
+6
-6
target/riscv/cpu.h
+3
-3
@@ -240,8 +240,8 @@ struct CPUArchState {
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uint64_t guest_phys_fault_addr;
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- target_ulong priv_ver;
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- target_ulong vext_ver;
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+ uint32_t priv_ver;
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+ uint32_t vext_ver;
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/* RISCVMXL, but uint32_t for vmstate migration */
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uint32_t misa_mxl; /* current mxl */
@@ -846,7 +846,7 @@ bool riscv_cpu_eff_priv(CPURISCVState *env, int *priv, bool *virt)
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}
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static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg,
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- target_long priv_ver,
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+ uint32_t priv_ver,
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uint32_t misa_ext)
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{
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/* In priv spec version 1.12 or newer, C always implies Zca */
target/riscv/machine.c
+2
-2
@@ -459,8 +459,8 @@ const VMStateDescription vmstate_riscv_cpu = {
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VMSTATE_UINT8(env.frm, RISCVCPU),
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VMSTATE_UINT64(env.badaddr, RISCVCPU),
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VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU),
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- VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
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- VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
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+ VMSTATE_UINT32(env.priv_ver, RISCVCPU),
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+ VMSTATE_UINT32(env.vext_ver, RISCVCPU),
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VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
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VMSTATE_UINT32(env.misa_ext, RISCVCPU),
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VMSTATE_UNUSED(4),
target/riscv/translate.c
+1
-1
@@ -59,7 +59,7 @@ typedef struct DisasContext {
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DisasContextBase base;
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target_ulong cur_insn_len;
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target_ulong pc_save;
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- target_ulong priv_ver;
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+ uint32_t priv_ver;
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RISCVMXL misa_mxl_max;
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RISCVMXL xl;
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RISCVMXL address_xl;