target/arm: Implement SVE BFSCALE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260826174213.614571-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:41 UTC
366ee9656e706d0694e3c359c840fa950d8b34cf
5 files changed
+14
-1
target/arm/cpu-features.h
+5
@@ -1585,6 +1585,11 @@ static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16);
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}
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+static inline bool isar_feature_aa64_sve_bfscale(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16) >= 2;
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+}
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+
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static inline bool isar_feature_aa64_ssve_fexpa(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SFEXPA);
target/arm/tcg/helper-sve-defs.h
+2
@@ -1303,6 +1303,8 @@ DEF_HELPER_FLAGS_6(sve_ah_fabd_s, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_6(sve_ah_fabd_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_6(sve_fscalbn_b16, TCG_CALL_NO_RWG,
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+ void, ptr, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG,
target/arm/tcg/sve.decode
+4
-1
@@ -1196,7 +1196,10 @@ FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
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FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
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}
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FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
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-FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
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+{
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+ BFSCALE 01100101 00 00 1001 100 ... ..... ..... @rdn_pg_rm_e0
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+ FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
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+}
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FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
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FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
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FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
target/arm/tcg/sve_helper.c
+1
@@ -4827,6 +4827,7 @@ DO_ZPZZ_FP(sve_ah_fabd_h, uint16_t, H1_2, ah_abd_h)
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DO_ZPZZ_FP(sve_ah_fabd_s, uint32_t, H1_4, ah_abd_s)
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DO_ZPZZ_FP(sve_ah_fabd_d, uint64_t, H1_8, ah_abd_d)
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+DO_ZPZZ_FP(sve_fscalbn_b16, int16_t, H1_2, bfloat16_scalbn)
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DO_ZPZZ_FP(sve_fscalbn_h, int16_t, H1_2, float16_scalbn)
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DO_ZPZZ_FP(sve_fscalbn_s, int32_t, H1_4, float32_scalbn)
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DO_ZPZZ_FP(sve_fscalbn_d, int64_t, H1_8, scalbn_d)
target/arm/tcg/translate-sve.c
+2
@@ -4515,6 +4515,8 @@ static gen_helper_gvec_4_ptr * const sve_fscalbn_zpzz_fns[4] = {
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};
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TRANS_FEAT(FSCALE, aa64_sme_or_sve, gen_gvec_fpst_arg_zpzz,
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sve_fscalbn_zpzz_fns[a->esz], a)
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+TRANS_FEAT(BFSCALE, aa64_sve_bfscale, gen_gvec_fpst_arg_zpzz,
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+ gen_helper_sve_fscalbn_b16, a)
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static gen_helper_gvec_4_ptr * const sve_fdiv_zpzz_fns[4] = {
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NULL,