target/arm/ptw: Flip sense of get_phys_addr return value
This completes the conversion of this family of functions to returning true on success and false on failure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260515142541.571911-15-peter.maydell@linaro.org
Peter Maydell committed
May 15, 2026 at 15:25 UTC
36b3f32642d10b8fd8003ff23d40917c8b27b4e7
4 files changed
+9
-9
target/arm/internals.h
+1
-1
@@ -1500,7 +1500,7 @@ typedef struct GetPhysAddrResult {
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* by doing a translation table walk on MMU based systems or using the
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* MPU state on MPU based systems.
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*
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- * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
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+ * Returns true if the translation was successful. Otherwise, phys_ptr, attrs,
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* prot and page_size may not be filled in, and the populated fsr value provides
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* information on why the translation aborted, in the format of a
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* DFSR/IFSR fault register, with the following caveats:
target/arm/ptw.c
+1
-1
@@ -3939,7 +3939,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
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.in_prot_check = 1 << access_type,
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};
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- return !get_phys_addr_gpc(env, &ptw, address, access_type,
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+ return get_phys_addr_gpc(env, &ptw, address, access_type,
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memop, result, fi);
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}
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target/arm/tcg/m_helper.c
+4
-4
@@ -222,7 +222,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
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int exc;
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bool exc_secure;
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- if (get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) {
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+ if (!get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) {
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/* MPU/SAU lookup failed */
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if (fi.type == ARMFault_QEMU_SFault) {
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if (mode == STACK_LAZYFP) {
@@ -311,7 +311,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
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bool exc_secure;
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uint32_t value;
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- if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) {
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+ if (!get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) {
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/* MPU/SAU lookup failed */
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if (fi.type == ARMFault_QEMU_SFault) {
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qemu_log_mask(CPU_LOG_INT,
@@ -2023,7 +2023,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
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"...really SecureFault with SFSR.INVEP\n");
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return false;
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}
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- if (get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) {
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+ if (!get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) {
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/* the MPU lookup failed */
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env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
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armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
@@ -2059,7 +2059,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
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ARMMMUFaultInfo fi = {};
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uint32_t value;
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- if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) {
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+ if (!get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) {
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/* MPU/SAU lookup failed */
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if (fi.type == ARMFault_QEMU_SFault) {
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qemu_log_mask(CPU_LOG_INT,
target/arm/tcg/tlb_helper.c
+3
-3
@@ -361,9 +361,9 @@ bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address,
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fi->type = ARMFault_Alignment;
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} else if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
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fi->type = ARMFault_Alignment;
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- } else if (!get_phys_addr(&cpu->env, address, access_type, memop,
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- core_to_arm_mmu_idx(&cpu->env, mmu_idx),
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- &res, fi)) {
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+ } else if (get_phys_addr(&cpu->env, address, access_type, memop,
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+ core_to_arm_mmu_idx(&cpu->env, mmu_idx),
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+ &res, fi)) {
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res.f.extra.arm.pte_attrs = res.cacheattrs.attrs;
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res.f.extra.arm.shareability = res.cacheattrs.shareability;
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*out = res.f;