target/arm: Implement FMLALB, FMLALT for AdvSIMD
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
379c3f5b29971ee7bb6a2385406b94dc43a80bd4
5 files changed
+138
target/arm/cpu-features.h
+5
@@ -1615,6 +1615,11 @@ static inline bool isar_feature_aa64_f8cvt(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8CVT);
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}
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+static inline bool isar_feature_aa64_f8fma(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8FMA);
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+}
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+
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/*
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* Combinations of feature tests, for ease of use with TRANS_FEAT.
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*/
target/arm/tcg/a64.decode
+8
@@ -25,6 +25,7 @@
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%esz_hsd 22:2 !function=xor_2
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%hl 11:1 21:1
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%hlm 11:1 20:2
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+%hlm4 11:1 19:3
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&r rn
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&rrr rd rn rm
@@ -38,6 +39,7 @@
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&rri_e rd rn imm esz
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&rrr_e rd rn rm esz
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&rrx_e rd rn rm idx esz
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+&rxx rd rn rm idxn idxm
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&rrrr_e rd rn rm ra esz
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&qrr_e q rd rn esz
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&qrri_e q rd rn imm esz
@@ -1215,6 +1217,9 @@ FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd
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FCVTN_bh 0.00 1110 010 ..... 11110 1 ..... ..... @qrrr_h
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FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... ..... @qrrr_h
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+FMLAL_hb_v 0 idxn:1 00 1110 110 rm:5 11111 1 rn:5 rd:5 \
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+ &rxx idxm=0
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+
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### Advanced SIMD scalar x indexed element
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FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
@@ -1333,6 +1338,9 @@ SQDMLAL_vi 0.00 1111 10 . ..... 0011 . 0 ..... ..... @qrrx_s
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SQDMLSL_vi 0.00 1111 01 .. .... 0111 . 0 ..... ..... @qrrx_h
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SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s
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+FMLAL_hb_vi 0 idxn:1 00 1111 11 ... rm:3 0000 . 0 rn:5 rd:5 \
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+ &rxx idxm=%hlm4
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+
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# Floating-point conditional select
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FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
target/arm/tcg/fp8_helper.c
+106
@@ -568,3 +568,109 @@ void HELPER(sme2_fcvtn_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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fp8_cvt_finish(env, &ctx);
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}
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+
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+typedef struct FP8MulContext {
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+ float_status stat;
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+ fp8_input_fn *fmt1;
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+ fp8_input_fn *fmt2;
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+ int scale;
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+} FP8MulContext;
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+
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+static FP8MulContext fp8_mul_start(CPUARMState *env, int scale_mask)
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+{
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+ uint64_t fpmr = env->vfp.fpmr;
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+
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+ FP8MulContext ret = {
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+ .stat = env->vfp.fp_status[FPST_A64],
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+ .fmt1 = fp8_input_fmt[FIELD_EX64(fpmr, FPMR, F8S1)],
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+ .fmt2 = fp8_input_fmt[FIELD_EX64(fpmr, FPMR, F8S2)],
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+ .scale = -(FIELD_EX64(fpmr, FPMR, LSCALE) & scale_mask),
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+ };
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+
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+ set_flush_to_zero(0, &ret.stat);
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+ set_flush_inputs_to_zero(0, &ret.stat);
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+ set_default_nan_mode(true, &ret.stat);
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+ set_float_rounding_mode(FIELD_EX64(fpmr, FPMR, OSM)
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+ ? float_round_nearest_even_max
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+ : float_round_nearest_even, &ret.stat);
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+
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+ /*
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+ * FP8 multiplies don't update any of the FPSR exception flags,
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+ * so we do not need an fp8_mul_finish() to propagate status
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+ * changes back from ret.stat into env->vfp.fp_status[].
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+ */
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+ return ret;
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+}
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+
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+static FloatParts64 f8dot(uint64_t a, uint64_t b, int n, FP8MulContext *ctx)
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+{
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+ /*
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+ * Because of default_nan_mode, NaNs need no special handling.
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+ * We'll simply get the default NaN out at the end of the sequence.
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+ */
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+ FloatParts64 p0 = ctx->fmt1(a & 0xff, &ctx->stat);
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+ FloatParts64 p1 = ctx->fmt2(b & 0xff, &ctx->stat);
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+ FloatParts64 pr = parts64_mul(&p0, &p1, &ctx->stat);
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+
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+ for (int i = 1; i < n; ++i) {
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+ p0 = ctx->fmt1(extract64(a, i * 8, 8), &ctx->stat);
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+ p1 = ctx->fmt2(extract64(b, i * 8, 8), &ctx->stat);
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+ pr = parts64_muladd(&p0, &p1, &pr, 0, &ctx->stat);
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+ }
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+ return parts64_scalbn(&pr, ctx->scale, &ctx->stat);
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+}
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+
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+static float16 f8dotadd_h(uint64_t a, uint64_t b, int n, float16 c,
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+ FP8MulContext *ctx)
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+{
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+ FloatParts64 p0 = f8dot(a, b, n, ctx);
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+ FloatParts64 p1 = float16_unpack_canonical(c, &ctx->stat);
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+
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+ p0 = parts64_addsub(&p0, &p1, &ctx->stat, false);
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+ return float16_round_pack_canonical(&p0, &ctx->stat);
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+}
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+
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+void HELPER(gvec_fmla_hb)(void *vd, void *vn, void *vm,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
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+ bool high = extract32(desc, SIMD_DATA_SHIFT, 1);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 2;
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+ uint8_t *n = vn;
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+ uint8_t *m = vm;
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+ float16 *d = vd;
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+
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+ for (size_t i = 0; i < nelem; i++) {
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+ uint8_t e0 = n[H1(2 * i + high)];
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+ uint8_t e1 = m[H1(2 * i + high)];
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+
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+ d[H2(i)] = f8dotadd_h(e0, e1, 1, d[H2(i)], &ctx);
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+ }
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+
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+ clear_tail(vd, oprsz, simd_maxsz(desc));
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+}
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+
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+void HELPER(gvec_fmla_idx_hb)(void *vd, void *vn, void *vm,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
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+ bool idx_n = extract32(desc, SIMD_DATA_SHIFT, 1);
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+ size_t idx_m = extract32(desc, SIMD_DATA_SHIFT + 2, 4);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 2;
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+ uint8_t *n = vn;
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+ uint8_t *m = vm;
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+ float16 *d = vd;
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+ size_t i = 0;
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+
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+ do {
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+ uint8_t e1 = m[2 * i + H1(idx_m)];
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+ do {
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+ uint8_t e0 = n[H1(2 * i + idx_n)];
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+ d[H2(i)] = f8dotadd_h(e0, e1, 1, d[H2(i)], &ctx);
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+ } while (++i % 8 != 0);
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+ } while (i < nelem);
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+
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+ clear_tail(vd, oprsz, simd_maxsz(desc));
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+}
target/arm/tcg/helper-fp8-defs.h
+3
@@ -23,3 +23,6 @@ DEF_HELPER_FLAGS_4(sve2_fcvtnb_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sve2_fcvtnt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sme2_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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+
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+DEF_HELPER_FLAGS_5(gvec_fmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_5(gvec_fmla_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
target/arm/tcg/translate-a64.c
+16
@@ -7481,6 +7481,22 @@ TRANS_FEAT(FMLSL_vi, aa64_fhm, do_fmlal_idx, a, true, false)
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TRANS_FEAT(FMLAL2_vi, aa64_fhm, do_fmlal_idx, a, false, true)
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TRANS_FEAT(FMLSL2_vi, aa64_fhm, do_fmlal_idx, a, true, true)
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+static bool do_fmla_fp8(DisasContext *s, arg_rxx *a,
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+ gen_helper_gvec_3_ptr *fn)
7486
+{
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+ if (fpmr_access_check(s) && fp_access_check(s)) {
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+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
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+ vec_full_reg_offset(s, a->rn),
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+ vec_full_reg_offset(s, a->rm),
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+ tcg_env, 16, vec_full_reg_size(s),
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+ a->idxn | (a->idxm << 2), fn);
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+ }
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+ return true;
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+}
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+
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+TRANS_FEAT(FMLAL_hb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)
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+TRANS_FEAT(FMLAL_hb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)
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+
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static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,
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gen_helper_gvec_3 * const fns[2])
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{