hw/misc: Add AX3000 clock control
This patch adds a new model for Axiado AX3000 clock control which supports to read ID and status Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com> Message-id: 20260713073033.3883619-3-kchiu@axiado.com [PMM: use HWADDR_PRIx] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Kuan-Jui Chiu committed
Aug 11, 2026 at 20:14 UTC
38b52563758ec3fe5df2ba8efa86b155ad79649d
4 files changed
+111
hw/misc/Kconfig
+3
@@ -257,4 +257,7 @@ config XLNX_VERSAL_TRNG
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config XLNX_ZYNQ_DDRC
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bool
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+config AXIADO_CLK
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+ bool
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+
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source macio/Kconfig
hw/misc/axiado_clk.c
new
+79
@@ -0,0 +1,79 @@
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+/*
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+ * Axiado Clock Control
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+ *
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+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "hw/misc/axiado_clk.h"
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+#include "qemu/log.h"
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+
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+#define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C
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+#define CLKRST_CPU_PLL_STS_OFFSET 0x14
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+
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+static uint64_t pll_read(void *opaque, hwaddr offset, unsigned size)
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+{
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+ switch (offset) {
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+ case CLKRST_CPU_PLL_POSTDIV_OFFSET:
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+ return 0x20891b;
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+ case CLKRST_CPU_PLL_STS_OFFSET:
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+ return 0x01;
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+ default:
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+ qemu_log_mask(LOG_UNIMP,
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+ "Register 0x%" HWADDR_PRIx " not implemented\n", offset);
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+ break;
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+ }
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+ return 0x00;
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+}
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+
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+static void pll_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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+{
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+ qemu_log_mask(LOG_UNIMP,
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+ "Register 0x%" HWADDR_PRIx " not implemented\n", offset);
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+}
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+
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+static const MemoryRegionOps pll_ops = {
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+ .read = pll_read,
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+ .write = pll_write,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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+ .impl = {
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+ .min_access_size = 4,
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+ .max_access_size = 4,
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+ },
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+ .valid = {
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+ .min_access_size = 4,
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+ .max_access_size = 4,
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+ }
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+};
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+
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+static void ax3000_clk_init(Object *obj)
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+{
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+ Ax3000ClkState *s = AX3000_CLK(obj);
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+
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+ memory_region_init_io(&s->pll_ctrl, obj, &pll_ops, s,
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+ TYPE_AX3000_CLK, AX3000_CLK_PLL_CTRL_SIZE);
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+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->pll_ctrl);
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+}
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+
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+static void ax3000_clk_class_init(ObjectClass *klass, const void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(klass);
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+
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+ dc->desc = "Axiado AX3000 Clock Control";
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+}
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+
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+static const TypeInfo ax3000_clk_info = {
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+ .parent = TYPE_SYS_BUS_DEVICE,
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+ .name = TYPE_AX3000_CLK,
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+ .instance_size = sizeof(Ax3000ClkState),
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+ .instance_init = ax3000_clk_init,
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+ .class_init = ax3000_clk_class_init,
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+};
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+
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+static void axiado_clk_register_type(void)
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+{
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+ type_register_static(&ax3000_clk_info);
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+}
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+type_init(axiado_clk_register_type);
hw/misc/meson.build
+3
@@ -1,4 +1,5 @@
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system_ss.add(when: 'CONFIG_APPLESMC', if_true: files('applesmc.c'))
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+
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system_ss.add(when: 'CONFIG_EDU', if_true: files('edu.c'))
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system_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('vmcoreinfo.c'))
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system_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c'))
@@ -168,3 +169,5 @@ system_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
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# HPPA devices
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system_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c'))
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+
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+system_ss.add(when: 'CONFIG_AXIADO_CLK', if_true: files('axiado_clk.c'))
include/hw/misc/axiado_clk.h
new
+26
@@ -0,0 +1,26 @@
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+/*
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+ * Axiado AX3000 Clock Control
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+ *
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+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#ifndef AXIADO_AX3000_CLK_H
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+#define AXIADO_AX3000_CLK_H
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+
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+#include "hw/core/sysbus.h"
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+#include "qom/object.h"
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+
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+#define TYPE_AX3000_CLK "ax3000-clk"
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+OBJECT_DECLARE_SIMPLE_TYPE(Ax3000ClkState, AX3000_CLK)
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+
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+#define AX3000_CLK_PLL_CTRL_SIZE 0x1000
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+
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+typedef struct Ax3000ClkState {
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+ SysBusDevice parent;
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+
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+ MemoryRegion pll_ctrl;
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+} Ax3000ClkState;
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+
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+#endif /* AXIADO_AX3000_CLK_H */