target/arm: Update SCR bits for Arm ARM M.a.a
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
394c4db5cfe52cb3f6f0f6b4af3dd365527d14f3
1 file changed
+11
target/arm/cpu.h
+11
@@ -1820,6 +1820,17 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
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#define SCR_AIEN (1ULL << 46)
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#define SCR_GPF (1ULL << 48)
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#define SCR_MECEN (1ULL << 49)
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+#define SCR_ENFPM (1ULL << 50)
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+#define SCR_TMEA (1ULL << 51)
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+#define SCR_TWERR (1ULL << 52)
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+#define SCR_PFAREN (1ULL << 53)
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+#define SCR_SRMASKEN (1ULL << 54)
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+#define SCR_ENIDCP128 (1ULL << 55)
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+#define SCR_DSE (1ULL << 57)
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+#define SCR_ENDSE (1ULL << 58)
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+#define SCR_FGTEN2 (1ULL << 59)
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+#define SCR_HDBSSEN (1ULL << 60)
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+#define SCR_HACDBSEN (1ULL << 61)
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#define SCR_NSE (1ULL << 62)
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/* GCSCR_ELx fields */