target/arm: Enable EnFPM bits for FEAT_FPMR
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
3a2ef816ee7c01c12842bac79f696b7468cd49e6
2 files changed
+12
target/arm/cpu.c
+3
@@ -742,6 +742,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
742
if (cpu_isar_feature(aa64_mec, cpu)) {
743
env->cp15.scr_el3 |= SCR_MECEN;
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}
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+ if (cpu_isar_feature(aa64_fpmr, cpu)) {
746
+ env->cp15.scr_el3 |= SCR_ENFPM;
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+ }
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}
749
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if (target_el == 2) {
target/arm/helper.c
+9
@@ -787,6 +787,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
787
if (cpu_isar_feature(aa64_mec, cpu)) {
788
valid_mask |= SCR_MECEN;
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}
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+ if (cpu_isar_feature(aa64_fpmr, cpu)) {
791
+ valid_mask |= SCR_ENFPM;
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+ }
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} else {
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valid_mask &= ~(SCR_RW | SCR_ST);
795
if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -3973,6 +3976,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
3976
if (cpu_isar_feature(aa64_gcs, cpu)) {
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valid_mask |= HCRX_GCSEN;
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}
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+ if (cpu_isar_feature(aa64_fpmr, cpu)) {
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+ valid_mask |= HCRX_ENFPM;
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+ }
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/* Clear RES0 bits. */
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env->cp15.hcrx_el2 = value & valid_mask;
@@ -4046,6 +4052,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env)
4052
if (cpu_isar_feature(aa64_gcs, cpu)) {
4053
hcrx |= HCRX_GCSEN;
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}
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+ if (cpu_isar_feature(aa64_fpmr, cpu)) {
4056
+ hcrx |= HCRX_ENFPM;
4057
+ }
4058
return hcrx;
4059
}
4060
if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) {