ati-vga: Latch src and dst pitch and offset on master_cntl default
Hardware testing on the Rage 128 confirms that (SRC/DST)_OFFSET, and (SRC/DST)_PITCH are latched when (SRC/DST)_PITCH_OFFSET_CNTL bits in DP_GUI_MASTER_CNTL are set to "default". The earlier approach looked at the state of the (SRC/DST)_PITCH_OFFSET_CNTL bits when offset and pitch registers were used. This meant that when (SRC/DST)_PITCH_OFFSET_CNTL was reset to "leave alone" the old values stored in the registers would return. This is not how the real hardware works. Signed-off-by: Chad Jablonski <chad@jablonski.xyz> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <20260303024730.1489136-5-chad@jablonski.xyz> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Chad Jablonski committed
Mar 2, 2026 at 21:47 UTC
3ab35ff519b95cb37e1f87281229ea68229daf58
2 files changed
+13
-9
hw/display/ati.c
+9
@@ -868,6 +868,15 @@ static void ati_mm_write(void *opaque, hwaddr addr,
868
s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 |
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(data & 0x4000) << 16;
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s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16;
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+
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+ if (!(data & GMC_SRC_PITCH_OFFSET_CNTL)) {
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+ s->regs.src_offset = s->regs.default_offset;
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+ s->regs.src_pitch = s->regs.default_pitch;
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+ }
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+ if (!(data & GMC_DST_PITCH_OFFSET_CNTL)) {
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+ s->regs.dst_offset = s->regs.default_offset;
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+ s->regs.dst_pitch = s->regs.default_pitch;
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+ }
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break;
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case DST_WIDTH_X:
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s->regs.dst_x = data & 0x3fff;
hw/display/ati_2d.c
+4
-9
@@ -43,8 +43,6 @@ static int ati_bpp_from_datatype(ATIVGAState *s)
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}
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}
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-#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
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-
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void ati_2d_blt(ATIVGAState *s)
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{
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/* FIXME it is probably more complex than this and may need to be */
@@ -63,13 +61,12 @@ void ati_2d_blt(ATIVGAState *s)
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n");
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return;
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}
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- int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
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+ int dst_stride = s->regs.dst_pitch;
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if (!dst_stride) {
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qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n");
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return;
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}
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- uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
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- s->regs.dst_offset : s->regs.default_offset);
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+ uint8_t *dst_bits = s->vga.vram_ptr + s->regs.dst_offset;
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
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dst_bits += s->regs.crtc_offset & 0x07ffffff;
@@ -97,14 +94,12 @@ void ati_2d_blt(ATIVGAState *s)
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s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
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unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
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s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
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- int src_stride = DEFAULT_CNTL ?
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- s->regs.src_pitch : s->regs.default_pitch;
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+ int src_stride = s->regs.src_pitch;
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if (!src_stride) {
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qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
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return;
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}
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- uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
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- s->regs.src_offset : s->regs.default_offset);
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+ uint8_t *src_bits = s->vga.vram_ptr + s->regs.src_offset;
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
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src_bits += s->regs.crtc_offset & 0x07ffffff;