hw/i3c/aspeed_i3c: Add more register fields
Adds the rest of the Aspeed I3C controller register fields. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
3adafff6a54c0fb8da112152ba7ef69579bc98a1
1 file changed
+42
-12
hw/i3c/aspeed_i3c.c
+42
-12
@@ -21,28 +21,58 @@
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/* I3C Controller Registers */
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REG32(I3C1_REG0, 0x10)
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REG32(I3C1_REG1, 0x14)
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- FIELD(I3C1_REG1, I2C_MODE, 0, 1)
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- FIELD(I3C1_REG1, SA_EN, 15, 1)
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+ FIELD(I3C1_REG1, I2C_MODE, 0, 1)
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+ FIELD(I3C1_REG1, SLV_TEST_MODE, 1, 1)
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+ FIELD(I3C1_REG1, ACT_MODE, 2, 2)
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+ FIELD(I3C1_REG1, PENDING_INT, 4, 4)
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+ FIELD(I3C1_REG1, SA, 8, 7)
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+ FIELD(I3C1_REG1, SA_EN, 15, 1)
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+ FIELD(I3C1_REG1, INST_ID, 16, 4)
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REG32(I3C2_REG0, 0x20)
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REG32(I3C2_REG1, 0x24)
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- FIELD(I3C2_REG1, I2C_MODE, 0, 1)
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- FIELD(I3C2_REG1, SA_EN, 15, 1)
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+ FIELD(I3C2_REG1, I2C_MODE, 0, 1)
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+ FIELD(I3C2_REG1, SLV_TEST_MODE, 1, 1)
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+ FIELD(I3C2_REG1, ACT_MODE, 2, 2)
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+ FIELD(I3C2_REG1, PENDING_INT, 4, 4)
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+ FIELD(I3C2_REG1, SA, 8, 7)
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+ FIELD(I3C2_REG1, SA_EN, 15, 1)
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+ FIELD(I3C2_REG1, INST_ID, 16, 4)
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REG32(I3C3_REG0, 0x30)
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REG32(I3C3_REG1, 0x34)
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- FIELD(I3C3_REG1, I2C_MODE, 0, 1)
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- FIELD(I3C3_REG1, SA_EN, 15, 1)
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+ FIELD(I3C3_REG1, I2C_MODE, 0, 1)
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+ FIELD(I3C3_REG1, SLV_TEST_MODE, 1, 1)
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+ FIELD(I3C3_REG1, ACT_MODE, 2, 2)
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+ FIELD(I3C3_REG1, PENDING_INT, 4, 4)
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+ FIELD(I3C3_REG1, SA, 8, 7)
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+ FIELD(I3C3_REG1, SA_EN, 15, 1)
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+ FIELD(I3C3_REG1, INST_ID, 16, 4)
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REG32(I3C4_REG0, 0x40)
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REG32(I3C4_REG1, 0x44)
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- FIELD(I3C4_REG1, I2C_MODE, 0, 1)
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- FIELD(I3C4_REG1, SA_EN, 15, 1)
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+ FIELD(I3C4_REG1, I2C_MODE, 0, 1)
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+ FIELD(I3C4_REG1, SLV_TEST_MODE, 1, 1)
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+ FIELD(I3C4_REG1, ACT_MODE, 2, 2)
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+ FIELD(I3C4_REG1, PENDING_INT, 4, 4)
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+ FIELD(I3C4_REG1, SA, 8, 7)
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+ FIELD(I3C4_REG1, SA_EN, 15, 1)
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+ FIELD(I3C4_REG1, INST_ID, 16, 4)
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REG32(I3C5_REG0, 0x50)
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REG32(I3C5_REG1, 0x54)
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- FIELD(I3C5_REG1, I2C_MODE, 0, 1)
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- FIELD(I3C5_REG1, SA_EN, 15, 1)
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+ FIELD(I3C5_REG1, I2C_MODE, 0, 1)
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+ FIELD(I3C5_REG1, SLV_TEST_MODE, 1, 1)
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+ FIELD(I3C5_REG1, ACT_MODE, 2, 2)
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+ FIELD(I3C5_REG1, PENDING_INT, 4, 4)
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+ FIELD(I3C5_REG1, SA, 8, 7)
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+ FIELD(I3C5_REG1, SA_EN, 15, 1)
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+ FIELD(I3C5_REG1, INST_ID, 16, 4)
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REG32(I3C6_REG0, 0x60)
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REG32(I3C6_REG1, 0x64)
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- FIELD(I3C6_REG1, I2C_MODE, 0, 1)
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- FIELD(I3C6_REG1, SA_EN, 15, 1)
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+ FIELD(I3C6_REG1, I2C_MODE, 0, 1)
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+ FIELD(I3C6_REG1, SLV_TEST_MODE, 1, 1)
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+ FIELD(I3C6_REG1, ACT_MODE, 2, 2)
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+ FIELD(I3C6_REG1, PENDING_INT, 4, 4)
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+ FIELD(I3C6_REG1, SA, 8, 7)
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+ FIELD(I3C6_REG1, SA_EN, 15, 1)
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+ FIELD(I3C6_REG1, INST_ID, 16, 4)
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static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size)
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{