hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API
In order to make the following commits easier to review, do not pre-initialize the reset_vec[] array, fill each word one by one. Set the start and FDT load addresses using the load/ store APIs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-ID: <20260527201348.29511-8-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philippe Mathieu-Daudé committed
May 27, 2026 at 22:13 UTC
3df0eb7feb1b0569167a67c7650bcb630897f719
1 file changed
+25
-30
hw/riscv/boot.c
+25
-30
@@ -18,6 +18,7 @@
18
*/
19
20
#include "qemu/osdep.h"
21
+#include "qemu/bswap.h"
22
#include "qemu/datadir.h"
23
#include "qemu/units.h"
24
#include "qemu/error-report.h"
@@ -444,6 +445,9 @@ void riscv_rom_copy_firmware_info(MachineState *machine,
445
&address_space_memory);
446
}
447
448
+#define CODE_WORDS 6
449
+#define DATA_WORDS 4
450
+
451
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
452
hwaddr start_addr,
453
hwaddr rom_base, hwaddr rom_size,
@@ -451,43 +455,34 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
455
uint64_t fdt_load_addr)
456
{
457
int i;
454
- uint32_t start_addr_hi32 = 0x00000000;
455
- uint32_t fdt_load_addr_hi32 = 0x00000000;
456
-
457
- if (!riscv_is_32bit(harts)) {
458
- start_addr_hi32 = start_addr >> 32;
459
- fdt_load_addr_hi32 = fdt_load_addr >> 32;
460
- }
461
- /* reset vector */
462
- uint32_t reset_vec[10] = {
463
- 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
464
- 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
465
- 0xf1402573, /* csrr a0, mhartid */
466
- 0,
467
- 0,
468
- 0x00028067, /* jr t0 */
469
- start_addr, /* start: .dword */
470
- start_addr_hi32,
471
- fdt_load_addr, /* fdt_laddr: .dword */
472
- fdt_load_addr_hi32,
473
- /* fw_dyn: */
474
- };
475
- if (riscv_is_32bit(harts)) {
476
- reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
477
- reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
458
+ const bool rv32 = riscv_is_32bit(harts);
459
+ uint32_t reset_vec[CODE_WORDS + DATA_WORDS];
460
+
461
+ /* .text */
462
+ reset_vec[0] = 0x00000297; /* 1: auipc t0, %pcrel_hi(fw_dyn) */
463
+ reset_vec[1] = 0x02828613; /* addi a2, t0, %pcrel_lo(1b) */
464
+ if (harts->harts[0].cfg.ext_zicsr) {
465
+ reset_vec[2] = 0xf1402573; /* csrr a0, mhartid */
466
} else {
479
- reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
480
- reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
481
- }
482
-
483
- if (!harts->harts[0].cfg.ext_zicsr) {
467
/*
468
* The Zicsr extension has been disabled, so let's ensure we don't
469
* run the CSR instruction. Let's fill the address with a non
470
* compressed nop.
471
*/
489
- reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */
472
+ reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */
473
+ }
474
+ if (rv32) {
475
+ reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
476
+ reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
477
+ } else {
478
+ reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
479
+ reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
480
}
481
+ reset_vec[5] = 0x00028067; /* jr t0 */
482
+
483
+ /* .data */
484
+ stq_p(&reset_vec[6], start_addr); /* start: .dword */
485
+ stq_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */
486
487
/* copy in the reset vector in little_endian byte order */
488
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {