target/arm: Implement MOVT (vector to table)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
3df4dbdad9333c3023d0ea0cde5ba16eb006c0b4
3 files changed
+25
target/arm/cpu-features.h
+5
@@ -1595,6 +1595,11 @@ static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64);
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}
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+static inline bool isar_feature_aa64_sme_lutv2(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, LUTv2);
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+}
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+
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static inline bool isar_feature_aa64_sme2(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) != 0;
target/arm/tcg/sme.decode
+2
@@ -141,6 +141,8 @@ MOVAZ_zt4 11000000 11 00011 0 v:1 .. 00110 za:3 zr:3 00 \
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MOVT_rzt 1100 0000 0100 1100 0 off:3 00 11111 rt:5
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MOVT_ztr 1100 0000 0100 1110 0 off:3 00 11111 rt:5
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+MOVT_ztz 1100 0000 0100 1111 00 off:2 00 11111 rt:5
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+
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### SME Memory
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&ldst esz rs pg rn rm za off v:bool st:bool
target/arm/tcg/translate-sme.c
+18
@@ -391,6 +391,24 @@ static bool do_movt(DisasContext *s, arg_MOVT_rzt *a,
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TRANS_FEAT(MOVT_rzt, aa64_sme2, do_movt, a, tcg_gen_ld_i64)
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TRANS_FEAT(MOVT_ztr, aa64_sme2, do_movt, a, tcg_gen_st_i64)
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+static bool trans_MOVT_ztz(DisasContext *s, arg_MOVT_ztz *a)
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+{
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+ if (!dc_isar_feature(aa64_sme_lutv2, s)) {
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+ return false;
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+ }
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+ if (sme_sm_enabled_check(s) && sme2_zt0_enabled_check(s)) {
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+ int svl = streaming_vec_reg_size(s);
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+ int tsize = MIN(svl, 64);
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+ int offset = (a->off % (64 / tsize)) * tsize;
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+
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+ tcg_gen_gvec_mov(MO_64,
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+ offsetof(CPUARMState, za_state.zt0) + offset,
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+ vec_full_reg_offset(s, a->rt), tsize,
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+ offset ? tsize : 64);
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+ }
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+ return true;
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+}
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+
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static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
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{
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typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i64);