hw/i2c/aspeed_i2c: Fix DMA64 address handling
The current code updates the upper 32 bits of dma_dram_offset only when aic->has_dma64 is false, which is incorrect. If aic->has_dma64 is true, the controller supports 64-bit DMA addressing and the upper 32-bit DMA address register must be used to update the dma_dram_offset accordingly. Fix the condition so that the upper 32 bits are updated only when 64-bit DMA is supported. Fixes: efea7ddb4689a1ac4bce63a9ddb32887c7f3ac50 ("hw/i2c/aspeed_i2c: Fix DMA moving data into incorrect address") Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260224073207.985162-1-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 24, 2026 at 07:32 UTC
402d5bf061393d08d2bcc76b3c0496f5b5d527dd
1 file changed
+2
-2
hw/i2c/aspeed_i2c.c
+2
-2
@@ -237,7 +237,7 @@ static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus *bus)
237
bus->dma_dram_offset =
238
deposit64(bus->dma_dram_offset, 0, 32,
239
FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR));
240
- if (!aic->has_dma64) {
240
+ if (aic->has_dma64) {
241
value = bus->regs[R_I2CM_DMA_TX_ADDR_HI];
242
bus->dma_dram_offset =
243
deposit64(bus->dma_dram_offset, 32, 32,
@@ -262,7 +262,7 @@ static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus *bus)
262
bus->dma_dram_offset =
263
deposit64(bus->dma_dram_offset, 0, 32,
264
FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR));
265
- if (!aic->has_dma64) {
265
+ if (aic->has_dma64) {
266
value = bus->regs[R_I2CM_DMA_RX_ADDR_HI];
267
bus->dma_dram_offset =
268
deposit64(bus->dma_dram_offset, 32, 32,