hw/riscv: Add macros and globals for simplifying machine definitions
Adds macros and global interfaces for defining machines available only in qemu-system-riscv32, qemu-system-riscv64, or both. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260520-hw-riscv-cpu-int-v3-3-d1123ea63d9c@rev.ng> [PMD: Constify InterfaceInfo] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Anton Johansson committed
Apr 30, 2025 at 13:44 UTC
40838c8251953a8f4a97af9f1dcc03a5eb0def41
2 files changed
+44
-1
include/hw/riscv/machines-qom.h
+26
@@ -17,4 +17,30 @@
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#define TYPE_TARGET_RISCV64_MACHINE \
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"target-info-riscv64-machine"
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+/*
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+ * Interfaces specifying whether a given QOM object is available in
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+ * qemu-system-riscv32, qemu-system-riscv64, or both.
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+ */
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+
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+extern const InterfaceInfo riscv32_machine_interfaces[];
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+extern const InterfaceInfo riscv64_machine_interfaces[];
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+extern const InterfaceInfo riscv32_64_machine_interfaces[];
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+
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+/*
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+ * Helper macros for defining machines available in qemu-system-riscv32,
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+ * qemu-system-riscv64, or both.
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+ */
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+
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+#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
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+ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
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+ riscv32_machine_interfaces)
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+
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+#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
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+ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
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+ riscv64_machine_interfaces)
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+
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+#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
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+ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
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+ riscv32_64_machine_interfaces)
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+
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#endif
target/riscv/machine.c
+18
-1
@@ -22,7 +22,8 @@
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#include "system/kvm.h"
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#include "migration/cpu.h"
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#include "exec/icount.h"
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-#include "debug.h"
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+#include "target/riscv/debug.h"
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+#include "hw/riscv/machines-qom.h"
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static bool pmp_needed(void *opaque)
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{
@@ -522,3 +523,19 @@ const VMStateDescription vmstate_riscv_cpu = {
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NULL
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}
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};
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+
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+const InterfaceInfo riscv32_machine_interfaces[] = {
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+ { TYPE_TARGET_RISCV32_MACHINE },
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+ { }
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+};
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+
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+const InterfaceInfo riscv64_machine_interfaces[] = {
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+ { TYPE_TARGET_RISCV64_MACHINE },
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+ { }
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+};
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+
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+const InterfaceInfo riscv32_64_machine_interfaces[] = {
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+ { TYPE_TARGET_RISCV32_MACHINE },
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+ { TYPE_TARGET_RISCV64_MACHINE },
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+ { }
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+};