target/riscv: Restore register dump zero padding
The register values lost their leading zeroes when the underlying type was changed, resulting in mismatched padding and harder to read output. Print with a runtime field width based on MXL, so values are 16 hex digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids adding target_ulong back into the dump. Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Max Chou <max.chou@sifive.com> Message-ID: <20260813032421.54438-1-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Joel Stanley committed
Aug 13, 2026 at 12:54 UTC
409c7d8682ae91c5e275d744d55a2ac19789534a
1 file changed
+6
-3
target/riscv/cpu.c
+6
-3
@@ -651,6 +651,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
651
{
652
RISCVCPU *cpu = RISCV_CPU(cs);
653
CPURISCVState *env = &cpu->env;
654
+ bool rv32 = riscv_cpu_is_32bit(cpu);
655
+ int width = rv32 ? 8 : 16;
656
+ uint64_t mask = rv32 ? UINT32_MAX : UINT64_MAX;
657
int i, j;
658
uint8_t *p;
659
@@ -665,7 +668,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
668
qemu_fprintf(f, " %-13s %d\n", "elp", env->elp);
669
}
670
#endif
668
- qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc);
671
+ qemu_fprintf(f, " %-13s %0*" PRIx64 "\n", "pc", width, env->pc & mask);
672
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
673
for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
674
int csrno = i;
@@ -692,8 +695,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
695
#endif
696
697
for (i = 0; i < 32; i++) {
695
- qemu_fprintf(f, " %-8s %" PRIx64,
696
- riscv_int_regnames[i], env->gpr[i]);
698
+ qemu_fprintf(f, " %-8s %0*" PRIx64,
699
+ riscv_int_regnames[i], width, env->gpr[i] & mask);
700
if ((i & 3) == 3) {
701
qemu_fprintf(f, "\n");
702
}