target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
41084b10c0d3c2d5b945f847321a98d52ee0ca41
3 files changed
+45
target/arm/cpu-features.h
+5
@@ -1570,6 +1570,11 @@ static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16);
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}
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+static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);
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+}
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+
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static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);
target/arm/tcg/sve.decode
+7
@@ -29,6 +29,7 @@
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%imm9_16_10 16:s6 10:3
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%size_23 23:2
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%dtype_23_13 23:2 13:2
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+%index4_19_10 19:2 10:2
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%index3_22_19 22:1 19:2
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%index3_22_17 22:1 17:2
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%index3_22_12 22:2 12:1
@@ -73,6 +74,7 @@
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&rri rd rn imm
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&rr_dbm rd rn dbm
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&rrri rd rn rm imm
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+&rxx rd rn rm idxn idxm
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&rri_esz rd rn imm esz
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&rrri_esz rd rn rm imm esz
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&rrr_esz rd rn rm esz
@@ -1864,6 +1866,8 @@ BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
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BFMLSLB_zzzw 01100100 11 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2
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BFMLSLT_zzzw 01100100 11 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2
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+FMLAL_hb 01100100 10 1 rm:5 100 idxn:1 10 rn:5 rd:5 &rxx idxm=0
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+
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### SVE2 floating-point dot-product
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FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
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BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
@@ -1880,6 +1884,9 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2
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BFMLSLB_zzxw 01100100 11 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2
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BFMLSLT_zzxw 01100100 11 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2
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+FMLAL_idx_hb 01100100 idxn:1 01 .. rm:3 0101 .. rn:5 rd:5 \
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+ &rxx idxm=%index4_19_10
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+
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### SVE2 floating-point dot-product (indexed)
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FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2
target/arm/tcg/translate-sve.c
+33
@@ -8355,3 +8355,36 @@ static bool trans_LUTI4_2h(DisasContext *s, arg_LUTI4_2h *a)
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}
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return true;
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}
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+
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+static bool do_fmla_fp8(DisasContext *s, arg_rxx *a, gen_helper_gvec_3_ptr *fn)
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+{
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+ bool fp8fma = dc_isar_feature(aa64_f8fma, s);
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+ bool ssve_fp8fma = dc_isar_feature(aa64_ssve_f8fma, s);
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+ bool ok = false;
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+
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+ /* Feature detection and enabling are complex here. */
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+ if (!(ssve_fp8fma || (fp8fma && dc_isar_feature(aa64_sve2, s)))) {
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+ return false;
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+ }
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+ if (fpmr_access_check(s)) {
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+ if (fp8fma) {
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+ s->is_nonstreaming = !ssve_fp8fma;
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+ ok = sve_access_check(s);
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+ } else {
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+ ok = sme_sm_enabled_check(s);
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+ }
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+ }
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+
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+ if (ok) {
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+ unsigned vsz = vec_full_reg_size(s);
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+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
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+ vec_full_reg_offset(s, a->rn),
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+ vec_full_reg_offset(s, a->rm),
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+ tcg_env, vsz, vsz,
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+ a->idxn | (a->idxm << 2), fn);
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+ }
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+ return true;
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+}
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+
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+TRANS(FMLAL_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)
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+TRANS(FMLAL_idx_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)