hw/arm/armsse: add Arm Corstone SSE-310
Add baseline Arm Corstone SSE-310 model. Device list changes between SSE-310 and SSE-300: New NPU0 Power Policy Unit and Configuration interface. All other devices are the same. Update comments in include/hw/arm/armsse.h to include SSE-300 and SSE-310 and their respective documentations. New SSE-310 IRQ mapping. sys_version and iidr values from the "SSE-310 with M85 and U55 FPGA" documentation for the mps3-an555. Refractor comments and code pertaining to both the SSE-300 and SSE-310. Arm Corstone SSE-310 TRM: https://developer.arm.com/documentation/102778/0000/ Reviewed-by: Owen Giles <owen.giles@hpe.com> Reviewed-by: Robert Elliott <elliott@hpe.com> Signed-off-by: Simon Xu <simonxhy0404@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260805153005.9989-3-simonxhy0404@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Simon Xu committed
Aug 17, 2026 at 19:26 UTC
41584d93f7d62d2d3c4b54e7f216ad6d2450f8a9
3 files changed
+211
-8
hw/arm/armsse.c
+202
-6
@@ -26,7 +26,7 @@
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#include "hw/core/qdev-clock.h"
27
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/*
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- * The SSE-300 puts some devices in different places to the
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+ * The SSE-300 and SSE-310 put some devices in different places to the
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* SSE-200 (and original IoTKit). We use an array of these structs
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* to define how each variant lays out these devices. (Parts of the
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* SoC that are the same for all variants aren't handled via these
@@ -118,6 +118,18 @@ static const Property sse300_properties[] = {
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DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
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};
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+static const Property sse310_properties[] = {
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+ DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
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+ MemoryRegion *),
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+ DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
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+ DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 21),
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+ DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
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+ DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
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+ DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
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+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
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+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
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+};
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+
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static const ARMSSEDeviceInfo iotkit_devices[] = {
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{
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.name = "timer0",
@@ -480,6 +492,146 @@ static const ARMSSEDeviceInfo sse300_devices[] = {
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}
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};
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+static const ARMSSEDeviceInfo sse310_devices[] = {
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+ {
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+ .name = "timer0",
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+ .type = TYPE_SSE_TIMER,
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+ .index = 0,
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+ .addr = 0x48000000,
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+ .ppc = 0,
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+ .ppc_port = 0,
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+ .irq = 3,
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+ },
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+ {
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+ .name = "timer1",
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+ .type = TYPE_SSE_TIMER,
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+ .index = 1,
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+ .addr = 0x48001000,
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+ .ppc = 0,
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+ .ppc_port = 1,
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+ .irq = 4,
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+ },
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+ {
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+ .name = "timer2",
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+ .type = TYPE_SSE_TIMER,
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+ .index = 2,
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+ .addr = 0x48002000,
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+ .ppc = 0,
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+ .ppc_port = 2,
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+ .irq = 5,
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+ },
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+ {
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+ .name = "timer3",
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+ .type = TYPE_SSE_TIMER,
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+ .index = 3,
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+ .addr = 0x48003000,
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+ .ppc = 0,
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+ .ppc_port = 5,
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+ .irq = 27,
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+ },
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+ {
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+ .name = "s32ktimer",
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+ .type = TYPE_CMSDK_APB_TIMER,
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+ .index = 0,
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+ .addr = 0x4802f000,
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+ .ppc = 1,
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+ .ppc_port = 0,
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+ .irq = 2,
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+ .slowclk = true,
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+ },
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+ {
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+ .name = "s32kwatchdog",
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+ .type = TYPE_CMSDK_APB_WATCHDOG,
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+ .index = 0,
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+ .addr = 0x5802e000,
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+ .ppc = NO_PPC,
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+ .irq = NMI_0,
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+ .slowclk = true,
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+ },
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+ {
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+ .name = "watchdog",
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+ .type = TYPE_UNIMPLEMENTED_DEVICE,
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+ .index = 0,
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+ .addr = 0x48040000,
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+ .size = 0x2000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "armsse-sysinfo",
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+ .type = TYPE_IOTKIT_SYSINFO,
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+ .index = 0,
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+ .addr = 0x48020000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "armsse-sysctl",
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+ .type = TYPE_IOTKIT_SYSCTL,
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+ .index = 0,
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+ .addr = 0x58021000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "SYS_PPU",
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+ .type = TYPE_UNIMPLEMENTED_DEVICE,
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+ .index = 1,
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+ .addr = 0x58022000,
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+ .size = 0x1000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "CPU0CORE_PPU",
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+ .type = TYPE_UNIMPLEMENTED_DEVICE,
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+ .index = 2,
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+ .addr = 0x58023000,
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+ .size = 0x1000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "MGMT_PPU",
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+ .type = TYPE_UNIMPLEMENTED_DEVICE,
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+ .index = 3,
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+ .addr = 0x58028000,
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+ .size = 0x1000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "DEBUG_PPU",
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+ .type = TYPE_UNIMPLEMENTED_DEVICE,
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+ .index = 4,
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+ .addr = 0x58029000,
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+ .size = 0x1000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "NPU0_PPU",
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+ .type = TYPE_UNIMPLEMENTED_DEVICE,
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+ .index = 5,
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+ .addr = 0x5802a000,
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+ .size = 0x1000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = "NPU0_CFG",
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+ .type = TYPE_UNIMPLEMENTED_DEVICE,
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+ .index = 6,
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+ .addr = 0x40004000,
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+ .size = 0x1000,
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+ .ppc = NO_PPC,
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+ .irq = NO_IRQ,
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+ },
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+ {
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+ .name = NULL,
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+ }
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+};
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+
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/* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
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static const bool sse200_irq_is_common[32] = {
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[0 ... 5] = true,
@@ -507,6 +659,20 @@ static const bool sse300_irq_is_common[32] = {
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/* 30, 31: reserved */
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};
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+static const bool sse310_irq_is_common[32] = {
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+ [0 ... 5] = true,
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+ /* 6-8: reserved */
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+ [9 ... 12] = true,
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+ /* 13: reserved */
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+ [14] = true,
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+ /* 15: reserved */
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+ [16] = true,
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+ /* 17-26: reserved */
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+ [27] = true,
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+ /* 28, 29: per-CPU CTI interrupts */
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+ /* 30, 31: reserved */
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+};
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+
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static const ARMSSEInfo armsse_variants[] = {
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{
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.name = TYPE_IOTKIT,
@@ -574,6 +740,28 @@ static const ARMSSEInfo armsse_variants[] = {
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.devinfo = sse300_devices,
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.irq_is_common = sse300_irq_is_common,
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},
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+ {
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+ .name = TYPE_SSE310,
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+ .sse_version = ARMSSE_SSE310,
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+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-m85"),
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+ .sram_banks = 2,
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+ .sram_bank_base = 0x21000000,
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+ .num_cpus = 1,
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+ .sys_version = 0x7e10043b,
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+ .iidr = 0x74e0043b,
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+ .cpuwait_rst = 0,
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+ .has_mhus = false,
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+ .has_cachectrl = false,
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+ .has_cpusecctrl = true,
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+ .has_cpuid = true,
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+ .has_cpu_pwrctrl = true,
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+ .has_sse_counter = true,
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+ .has_tcms = true,
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+ .props = sse310_properties,
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+ .props_count = ARRAY_SIZE(sse310_properties),
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+ .devinfo = sse310_devices,
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+ .irq_is_common = sse310_irq_is_common,
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+ }
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};
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static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
@@ -604,6 +792,14 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
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sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
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sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */
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break;
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+ case ARMSSE_SSE310:
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+ sys_config = 0;
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+ sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
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+ sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
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+ sys_config = deposit32(sys_config, 10, 1, 0); /* No CoreSight SoC */
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+ sys_config = deposit32(sys_config, 11, 2, 0); /* Basic level PI */
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+ sys_config = deposit32(sys_config, 16, 3, 4); /* CPU0 = Cortex-M85 */
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+ break;
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default:
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g_assert_not_reached();
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}
@@ -1205,7 +1401,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
1401
qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
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qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
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1208
- /* The SSE-300 has a System Counter / System Timestamp Generator */
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+ /* The SSE-300/SSE-310 has a System Counter / System Timestamp Generator */
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if (info->has_sse_counter) {
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sse_counter);
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@@ -1225,12 +1421,12 @@ static void armsse_realize(DeviceState *dev, Error **errp)
1421
}
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if (info->has_tcms) {
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- /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000 */
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- memory_region_init_ram(&s->itcm, NULL, "sse300-itcm", 512 * KiB, errp);
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+ /* SSE-300/SSE-310 have ITCM at 0x0000_0000 and DTCM at 0x2000_0000 */
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+ memory_region_init_ram(&s->itcm, NULL, "itcm", 512 * KiB, errp);
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if (*errp) {
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return;
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}
1233
- memory_region_init_ram(&s->dtcm, NULL, "sse300-dtcm", 512 * KiB, errp);
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+ memory_region_init_ram(&s->dtcm, NULL, "dtcm", 512 * KiB, errp);
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if (*errp) {
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return;
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}
@@ -1461,7 +1657,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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* 0x50010000: L1 icache control registers
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* 0x50011000: CPUSECCTRL (CPU local security control registers)
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* 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
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- * The SSE-300 has an extra:
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+ * The SSE-300 and SSE-310 have an extra:
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* 0x40012000 and 0x50012000: CPU_PWRCTRL register block
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*/
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if (info->has_cachectrl) {
include/hw/arm/armsse-version.h
+2
@@ -25,6 +25,7 @@ enum {
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ARMSSE_IOTKIT = 0,
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ARMSSE_SSE200 = 200,
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ARMSSE_SSE300 = 300,
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+ ARMSSE_SSE310 = 310
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};
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static inline bool armsse_version_valid(uint32_t sse_version)
@@ -33,6 +34,7 @@ static inline bool armsse_version_valid(uint32_t sse_version)
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case ARMSSE_IOTKIT:
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case ARMSSE_SSE200:
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case ARMSSE_SSE300:
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+ case ARMSSE_SSE310:
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return true;
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default:
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return false;
include/hw/arm/armsse.h
+7
-2
@@ -11,12 +11,16 @@
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/*
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* This is a model of the Arm "Subsystems for Embedded" family of
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- * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
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- * SSE-200. Currently we model:
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+ * hardware, which include the IoT Kit and the SSE-050, SSE-100,
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+ * SSE-200, SSE-300, and SSE-310. Currently we model:
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* - the Arm IoT Kit which is documented in
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* https://developer.arm.com/documentation/ecm0601256/latest
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* - the SSE-200 which is documented in
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* https://developer.arm.com/documentation/101104/latest/
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+ * - the SSE-300 which is documented in
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+ * https://support.arm.com/documentation/101773/latest/
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+ * - the SSE-310 which is documented in
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+ * https://support.arm.com/documentation/102778/latest/
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*
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* The IoTKit contains:
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* a Cortex-M33
@@ -127,6 +131,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
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#define TYPE_IOTKIT "iotkit"
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#define TYPE_SSE200 "sse-200"
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#define TYPE_SSE300 "sse-300"
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+#define TYPE_SSE310 "sse-310"
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/* We have an IRQ splitter and an OR gate input for each external PPC
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* and the 2 internal PPCs