target/hexagon: Add implementation of cycle counters
Add cycle counting infrastructure for system emulation: - PCYCLE_ENABLED TB flag to gate cycle counting - gen_pcycle_counters() to emit cycle count increments - Real implementations replacing pcycle stubs in cpu_helper.c - hex_cycle_count TCG global for t_cycle_count - pcycle_enabled context field in DisasContext All pcycle code is guarded by #ifndef CONFIG_USER_ONLY. Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jun 22, 2026 at 15:28 UTC
418376351d05dfb8abf4074ad10e26dd2a2e035f
5 files changed
+45
-3
target/hexagon/cpu.c
+4
@@ -268,6 +268,10 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs)
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hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);
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}
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+#ifndef CONFIG_USER_ONLY
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+ hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1);
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+#endif
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+
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return (TCGTBCPUState){ .pc = pc, .flags = hex_flags };
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}
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target/hexagon/cpu.h
+1
@@ -164,6 +164,7 @@ struct ArchCPU {
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#include "cpu_bits.h"
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FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
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+FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1)
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G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
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uint32_t exception,
target/hexagon/cpu_helper.c
+11
-3
@@ -33,17 +33,25 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index)
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uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env)
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{
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- g_assert_not_reached();
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+ uint64_t total = 0;
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+ CPUState *cs;
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+
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+ g_assert(bql_locked());
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+ CPU_FOREACH(cs) {
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+ CPUHexagonState *thread_env = cpu_env(cs);
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+ total += thread_env->t_cycle_count;
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+ }
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+ return total;
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}
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uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env)
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{
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- g_assert_not_reached();
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+ return (uint32_t)(hexagon_get_sys_pcycle_count(env) >> 32);
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}
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uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env)
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{
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- g_assert_not_reached();
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+ return (uint32_t)(hexagon_get_sys_pcycle_count(env));
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}
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void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val)
target/hexagon/translate.c
+26
@@ -61,6 +61,9 @@ TCGv_i64 hex_store_val64[STORES_MAX];
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TCGv hex_llsc_addr;
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TCGv hex_llsc_val;
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TCGv_i64 hex_llsc_val_i64;
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+#ifndef CONFIG_USER_ONLY
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+TCGv_i64 hex_cycle_count;
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+#endif
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TCGv hex_vstore_addr[VSTORES_MAX];
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TCGv hex_vstore_size[VSTORES_MAX];
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TCGv hex_vstore_pending[VSTORES_MAX];
@@ -128,6 +131,15 @@ static void gen_exception_raw(int excp)
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gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
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}
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+#ifndef CONFIG_USER_ONLY
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+static void gen_pcycle_counters(DisasContext *ctx)
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+{
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+ if (ctx->pcycle_enabled) {
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+ tcg_gen_addi_i64(hex_cycle_count, hex_cycle_count, ctx->num_cycles);
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+ }
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+}
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+#endif
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+
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static void gen_exec_counters(DisasContext *ctx)
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{
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
@@ -136,6 +148,9 @@ static void gen_exec_counters(DisasContext *ctx)
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hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT],
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hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns);
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+#ifndef CONFIG_USER_ONLY
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+ gen_pcycle_counters(ctx);
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+#endif
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}
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static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
@@ -810,6 +825,8 @@ static void gen_commit_hvx(DisasContext *ctx)
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}
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}
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+#define PCYCLES_PER_PACKET 1
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+
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static void update_exec_counters(DisasContext *ctx)
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{
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int num_real_insns = 0;
@@ -829,6 +846,7 @@ static void update_exec_counters(DisasContext *ctx)
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ctx->num_packets++;
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ctx->num_insns += num_real_insns;
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ctx->num_hvx_insns += num_hvx_insns;
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+ ctx->num_cycles += PCYCLES_PER_PACKET;
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}
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static void gen_commit_packet(DisasContext *ctx)
@@ -978,6 +996,10 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,
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ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);
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ctx->short_circuit = hex_cpu->short_circuit;
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ctx->hex_def = HEXAGON_CPU_GET_CLASS(hex_cpu)->hex_def;
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+#ifndef CONFIG_USER_ONLY
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+ ctx->num_cycles = 0;
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+ ctx->pcycle_enabled = FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED);
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+#endif
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}
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static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
@@ -1121,6 +1143,10 @@ void hexagon_translate_init(void)
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offsetof(CPUHexagonState, llsc_val), "llsc_val");
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hex_llsc_val_i64 = tcg_global_mem_new_i64(tcg_env,
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offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
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+#ifndef CONFIG_USER_ONLY
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+ hex_cycle_count = tcg_global_mem_new_i64(tcg_env,
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+ offsetof(CPUHexagonState, t_cycle_count), "t_cycle_count");
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+#endif
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for (i = 0; i < STORES_MAX; i++) {
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snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
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hex_store_addr[i] = tcg_global_mem_new(tcg_env,
target/hexagon/translate.h
+3
@@ -85,6 +85,9 @@ typedef struct DisasContext {
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TCGv new_pred_value[NUM_PREGS];
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TCGv branch_taken;
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TCGv dczero_addr;
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+ bool pcycle_enabled;
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+ bool pkt_ends_tb;
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+ uint32_t num_cycles;
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} DisasContext;
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bool is_gather_store_insn(DisasContext *ctx);