@samitouri / QOSamiQemu / commits / 42031f21f9

disas/riscv: Set dec->opcode_data in decode function

This allows each opcode table to be private to the decode file. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-10-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Richard Henderson committed Aug 12, 2026 at 15:30 UTC 42031f21f9c8ee999dc6a1b1589a753df47bde37
7 files changed +34 -26
disas/riscv-xlrbr.c
+3 -1
@@ -24,7 +24,7 @@ typedef enum {
24 rv_op_crc32c_d = 8,
25 } rv_xlrbr_op;
26
27 -const rv_opcode_data rv_xlrbr_opcode_data[] = {
27 +static const rv_opcode_data xlrbr_opcode_data[] = {
28 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
29 { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
30 { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
@@ -75,5 +75,7 @@ void decode_xlrbr(rv_decode *dec, rv_isa isa)
75 }
76 break;
77 }
78 +
79 + dec->opcode_data = xlrbr_opcode_data;
80 dec->op = op;
81 }
disas/riscv-xlrbr.h
-2
@@ -12,8 +12,6 @@
12
13 #include "disas/riscv.h"
14
15 -extern const rv_opcode_data rv_xlrbr_opcode_data[];
16 -
15 void decode_xlrbr(rv_decode *, rv_isa);
16
17 #endif /* DISAS_RISCV_XLRBR_H */
disas/riscv-xthead.c
+12 -1
@@ -127,7 +127,7 @@ typedef enum {
127 rv_op_th_sync_s,
128 } rv_xthead_op;
129
130 -const rv_opcode_data xthead_opcode_data[] = {
130 +static const rv_opcode_data xthead_opcode_data[] = {
131 { "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
132 /* XTheadBa */
133 { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
@@ -272,6 +272,7 @@ void decode_xtheadba(rv_decode *dec, rv_isa isa)
272 break;
273 }
274
275 + dec->opcode_data = xthead_opcode_data;
276 dec->op = op;
277 }
278
@@ -330,6 +331,7 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)
331 break;
332 }
333
334 + dec->opcode_data = xthead_opcode_data;
335 dec->op = op;
336 }
337
@@ -356,6 +358,7 @@ void decode_xtheadbs(rv_decode *dec, rv_isa isa)
358 break;
359 }
360
361 + dec->opcode_data = xthead_opcode_data;
362 dec->op = op;
363 }
364
@@ -434,6 +437,7 @@ void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
437 break;
438 }
439
440 + dec->opcode_data = xthead_opcode_data;
441 dec->op = op;
442 }
443
@@ -461,6 +465,7 @@ void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
465 break;
466 }
467
468 + dec->opcode_data = xthead_opcode_data;
469 dec->op = op;
470 }
471
@@ -498,6 +503,7 @@ void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
503 break;
504 }
505
506 + dec->opcode_data = xthead_opcode_data;
507 dec->op = op;
508 }
509
@@ -533,6 +539,7 @@ void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
539 break;
540 }
541
542 + dec->opcode_data = xthead_opcode_data;
543 dec->op = op;
544 }
545
@@ -564,6 +571,7 @@ void decode_xtheadmac(rv_decode *dec, rv_isa isa)
571 break;
572 }
573
574 + dec->opcode_data = xthead_opcode_data;
575 dec->op = op;
576 }
577
@@ -638,6 +646,7 @@ void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
646 break;
647 }
648
649 + dec->opcode_data = xthead_opcode_data;
650 dec->op = op;
651 }
652
@@ -672,6 +681,7 @@ void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
681 break;
682 }
683
684 + dec->opcode_data = xthead_opcode_data;
685 dec->op = op;
686 }
687
@@ -706,5 +716,6 @@ void decode_xtheadsync(rv_decode *dec, rv_isa isa)
716 break;
717 }
718
719 + dec->opcode_data = xthead_opcode_data;
720 dec->op = op;
721 }
disas/riscv-xthead.h
-2
@@ -11,8 +11,6 @@
11
12 #include "disas/riscv.h"
13
14 -extern const rv_opcode_data xthead_opcode_data[];
15 -
14 void decode_xtheadba(rv_decode *, rv_isa);
15 void decode_xtheadbb(rv_decode *, rv_isa);
16 void decode_xtheadbs(rv_decode *, rv_isa);
disas/riscv-xventana.c
+2 -1
@@ -14,7 +14,7 @@ typedef enum {
14 ventana_op_vt_maskcn = 2,
15 } rv_ventana_op;
16
17 -const rv_opcode_data ventana_opcode_data[] = {
17 +static const rv_opcode_data ventana_opcode_data[] = {
18 { "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
19 { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
20 { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
@@ -38,5 +38,6 @@ void decode_xventanacondops(rv_decode *dec, rv_isa isa)
38 break;
39 }
40
41 + dec->opcode_data = ventana_opcode_data;
42 dec->op = op;
43 }
disas/riscv-xventana.h
-2
@@ -11,8 +11,6 @@
11
12 #include "disas/riscv.h"
13
14 -extern const rv_opcode_data ventana_opcode_data[];
15 -
14 void decode_xventanacondops(rv_decode*, rv_isa);
15
16 #endif /* DISAS_RISCV_XVENTANA_H */
disas/riscv.c
+17 -17
@@ -1656,7 +1656,7 @@ static uint32_t operand_lpl(rv_inst inst)
1656
1657 /* instruction metadata */
1658
1659 -const rv_opcode_data rvi_opcode_data[] = {
1659 +static const rv_opcode_data rvi_opcode_data[] = {
1660 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
1661 { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
1662 { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
@@ -2948,6 +2948,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
2948 {
2949 rv_inst inst = dec->inst;
2950 rv_opcode op = rv_op_illegal;
2951 +
2952 switch ((inst >> 0) & 0b11) {
2953 case 0:
2954 switch ((inst >> 13) & 0b111) {
@@ -4590,6 +4591,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
4591 }
4592 break;
4593 }
4594 +
4595 + dec->opcode_data = rvi_opcode_data;
4596 dec->op = op;
4597 }
4598
@@ -5421,33 +5424,30 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
5424 };
5425 const rv_opcode_data *op;
5426
5424 - dec.opcode_data = rvi_opcode_data;
5427 decode_inst_opcode(&dec, isa);
5428
5429 if (dec.op == rv_op_illegal && cfg) {
5430 static const struct {
5431 bool (*guard_func)(const RISCVCPUConfig *);
5430 - const rv_opcode_data *opcode_data;
5432 void (*decode_func)(rv_decode *, rv_isa);
5433 } decoders[] = {
5433 - { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
5434 - { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
5435 - { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
5436 - { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
5437 - { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
5438 - { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
5439 - { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
5440 - { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
5441 - { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
5442 - { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
5443 - { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
5444 - { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
5445 - { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
5434 + { has_xtheadba_p, decode_xtheadba },
5435 + { has_xtheadbb_p, decode_xtheadbb },
5436 + { has_xtheadbs_p, decode_xtheadbs },
5437 + { has_xtheadcmo_p, decode_xtheadcmo },
5438 + { has_xtheadcondmov_p, decode_xtheadcondmov },
5439 + { has_xtheadfmemidx_p, decode_xtheadfmemidx },
5440 + { has_xtheadfmv_p, decode_xtheadfmv },
5441 + { has_xtheadmac_p, decode_xtheadmac },
5442 + { has_xtheadmemidx_p, decode_xtheadmemidx },
5443 + { has_xtheadmempair_p, decode_xtheadmempair },
5444 + { has_xtheadsync_p, decode_xtheadsync },
5445 + { has_XVentanaCondOps_p, decode_xventanacondops },
5446 + { has_xlrbr_p, decode_xlrbr },
5447 };
5448
5449 for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
5450 if (decoders[i].guard_func(cfg)) {
5450 - dec.opcode_data = decoders[i].opcode_data;
5451 decoders[i].decode_func(&dec, isa);
5452 if (dec.op != rv_op_illegal) {
5453 break;