hw/riscv: Connect K230 DDR controller and PHY models
Replace the unimplemented K230 DDR configuration region with the DDRC model and map the PHY model at 0x9a000000. Connect the controller to the PHY so DFI status reflects PHY training and initialization state. Suggested-by: Chao Liu <chao.liu@processmission.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Signed-off-by: Junze Cao <caojunze424@gmail.com> Message-ID: <20260807-k230-ddr-v2-v2-2-c531308ae819@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Junze Cao committed
Aug 7, 2026 at 18:21 UTC
4309ee8e915d37763813ad4406d7f67a0fd08324
3 files changed
+24
-3
docs/system/riscv/k230.rst
+4
@@ -20,12 +20,16 @@ The ``k230`` machine supports the following devices:
20
* Platform-Level Interrupt Controller (PLIC)
21
* 2 K230 Watchdog Timer
22
* 5 UART
23
+* K230 DDRC CFG and DDR PHY
24
25
Boot options
26
------------
27
The ``k230`` machine supports K230 SDK boot through M-mode U-Boot, which then
28
starts OpenSBI/Linux with ``bootm``. It also supports direct Linux boot.
29
30
+The DDRC CFG and DDR PHY models allow the K230 SDK U-Boot SPL to complete DDR
31
+initialization before loading the next boot stage.
32
+
33
K230 SDK Linux kernels use T-HEAD C9xx private MAEE page table attributes. QEMU
34
does not implement MAEE in the generic RISC-V MMU, so such kernels need to be
35
built with standard RISC-V PTE bits before they can boot under QEMU.
hw/riscv/k230.c
+16
-3
@@ -97,6 +97,7 @@ static const MemMapEntry memmap[] = {
97
[K230_DEV_SPI] = { 0x91584000, 0x00001000 },
98
[K230_DEV_HI_SYS_CFG] = { 0x91585000, 0x00000400 },
99
[K230_DEV_DDRC_CFG] = { 0x98000000, 0x02000000 },
100
+ [K230_DEV_DDR_PHY] = { 0x9A000000, 0x00400000 },
101
[K230_DEV_FLASH] = { 0xC0000000, 0x08000000 },
102
[K230_DEV_PLIC] = { 0xF00000000, 0x00400000 },
103
[K230_DEV_CLINT] = { 0xF04000000, 0x00400000 },
@@ -108,6 +109,11 @@ static void k230_soc_init(Object *obj)
109
RISCVHartArrayState *cpu0 = &s->c908_cpu;
110
111
object_initialize_child(obj, "c908-cpu", cpu0, TYPE_RISCV_HART_ARRAY);
112
+ object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
113
+ TYPE_K230_DDR_CFG);
114
+ object_initialize_child(obj, "ddr-phy", &s->ddr_phy,
115
+ TYPE_K230_DDR_PHY);
116
+ s->ddr_cfg.phy = &s->ddr_phy;
117
object_initialize_child(obj, "k230-wdt0", &s->wdt[0], TYPE_K230_WDT);
118
object_initialize_child(obj, "k230-wdt1", &s->wdt[1], TYPE_K230_WDT);
119
@@ -158,6 +164,16 @@ static void k230_soc_realize(DeviceState *dev, Error **errp)
164
int c908_cpus;
165
166
sysbus_realize(SYS_BUS_DEVICE(&s->c908_cpu), &error_fatal);
167
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp)) {
168
+ return;
169
+ }
170
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_phy), errp)) {
171
+ return;
172
+ }
173
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
174
+ memmap[K230_DEV_DDRC_CFG].base);
175
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_phy), 0,
176
+ memmap[K230_DEV_DDR_PHY].base);
177
178
c908_cpus = s->c908_cpu.num_harts;
179
@@ -361,9 +377,6 @@ static void k230_soc_realize(DeviceState *dev, Error **errp)
377
create_unimplemented_device("hi_sys_cfg", memmap[K230_DEV_HI_SYS_CFG].base,
378
memmap[K230_DEV_HI_SYS_CFG].size);
379
364
- create_unimplemented_device("ddrc_cfg", memmap[K230_DEV_DDRC_CFG].base,
365
- memmap[K230_DEV_DDRC_CFG].size);
366
-
380
create_unimplemented_device("flash", memmap[K230_DEV_FLASH].base,
381
memmap[K230_DEV_FLASH].size);
382
}
include/hw/riscv/k230.h
+4
@@ -16,6 +16,7 @@
16
#define HW_K230_H
17
18
#include "hw/core/boards.h"
19
+#include "hw/misc/k230_ddr.h"
20
#include "hw/riscv/riscv_hart.h"
21
#include "hw/watchdog/k230_wdt.h"
22
@@ -32,6 +33,8 @@ typedef struct K230SoCState {
33
/*< public >*/
34
RISCVHartArrayState c908_cpu; /* Small core */
35
36
+ K230DDRCfgState ddr_cfg;
37
+ K230DDRPhyState ddr_phy;
38
K230WdtState wdt[2];
39
MemoryRegion sram;
40
MemoryRegion bootrom;
@@ -112,6 +115,7 @@ enum {
115
K230_DEV_SPI,
116
K230_DEV_HI_SYS_CFG,
117
K230_DEV_DDRC_CFG,
118
+ K230_DEV_DDR_PHY,
119
K230_DEV_FLASH,
120
K230_DEV_PLIC,
121
K230_DEV_CLINT,