hw/arm/aspeed: Convert SRAM size definition to array type
Prepare the Aspeed SoC model for future platforms that may contain multiple SRAM regions with different sizes and MMIO mappings. The current implementation stores SRAM size information in a single sram_size field, which limits extensibility when additional SRAM instances are introduced. Convert sram_size into an array-based definition and update all existing users to reference sram_size[0]. This aligns with the previous SRAM MemoryRegion array conversion and provides a scalable foundation for supporting multiple SRAM regions in future SoCs. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
May 25, 2026 at 05:30 UTC
43eaa304c16d1ebb1280088cfae1e6037d77f41e
5 files changed
+14
-14
hw/arm/aspeed_ast10x0.c
+4
-4
@@ -240,8 +240,8 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
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/* Internal SRAM */
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sram_name = g_strdup_printf("aspeed.sram.%d",
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CPU(a->armv7m.cpu)->cpu_index);
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- memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, sc->sram_size,
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- &err);
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+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
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+ sc->sram_size[0], &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return false;
@@ -493,7 +493,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST1030_A1_SILICON_REV;
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- sc->sram_size = 0xc0000;
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+ sc->sram_size[0] = 0xc0000;
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sc->secsram_size = 0x40000; /* 256 * KiB */
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sc->spis_num = 2;
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sc->ehcis_num = 0;
@@ -521,7 +521,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST1060_A2_SILICON_REV;
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- sc->sram_size = 0xc0000;
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+ sc->sram_size[0] = 0xc0000;
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sc->secsram_size = 0x40000; /* 256 * KiB */
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sc->spis_num = 2;
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sc->wdts_num = 4;
hw/arm/aspeed_ast2400.c
+3
-3
@@ -282,7 +282,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
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/* SRAM */
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sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
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if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
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- sc->sram_size, errp)) {
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+ sc->sram_size[0], errp)) {
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return;
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}
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memory_region_add_subregion(s->memory,
@@ -533,7 +533,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data)
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2400_A1_SILICON_REV;
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- sc->sram_size = 0x8000;
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+ sc->sram_size[0] = 0x8000;
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sc->spis_num = 1;
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sc->ehcis_num = 1;
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sc->wdts_num = 2;
@@ -560,7 +560,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data)
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2500_A1_SILICON_REV;
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- sc->sram_size = 0x9000;
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+ sc->sram_size[0] = 0x9000;
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sc->spis_num = 2;
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sc->ehcis_num = 2;
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sc->wdts_num = 3;
hw/arm/aspeed_ast2600.c
+2
-2
@@ -438,7 +438,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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/* SRAM */
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sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
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if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
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- sc->sram_size, errp)) {
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+ sc->sram_size[0], errp)) {
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return;
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}
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memory_region_add_subregion(s->memory,
@@ -764,7 +764,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data)
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2600_A3_SILICON_REV;
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- sc->sram_size = 0x16400;
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+ sc->sram_size[0] = 0x16400;
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sc->spis_num = 2;
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sc->ehcis_num = 2;
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sc->wdts_num = 4;
hw/arm/aspeed_ast27x0.c
+4
-4
@@ -778,8 +778,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
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/* SRAM */
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name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
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- if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, sc->sram_size,
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- errp)) {
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+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name,
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+ sc->sram_size[0], errp)) {
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return;
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}
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memory_region_add_subregion(s->memory,
@@ -1151,7 +1151,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2700_A1_SILICON_REV;
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- sc->sram_size = 0x20000;
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+ sc->sram_size[0] = 0x20000;
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sc->pcie_num = 3;
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sc->spis_num = 3;
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sc->sgpio_num = 2;
@@ -1181,7 +1181,7 @@ static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data)
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2700_A2_SILICON_REV;
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- sc->sram_size = 0x20000;
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+ sc->sram_size[0] = 0x20000;
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sc->pcie_num = 3;
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sc->spis_num = 3;
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sc->sgpio_num = 2;
include/hw/arm/aspeed_soc.h
+1
-1
@@ -172,7 +172,7 @@ struct AspeedSoCClass {
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/** valid_cpu_types: NULL terminated array of a single CPU type. */
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const char * const *valid_cpu_types;
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uint32_t silicon_rev;
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- uint64_t sram_size;
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+ uint64_t sram_size[ASPEED_SRAM_NUM];
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uint64_t secsram_size;
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int pcie_num;
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int spis_num;