target/arm: Enable FEAT_SVE_BFSCALE for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260826174213.614571-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:42 UTC
44230b9fc51ec44c689b344c4b295cb546474f2b
3 files changed
+3
-1
docs/system/arm/emulation.rst
+1
@@ -199,6 +199,7 @@ the following architecture extensions:
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- FEAT_SVE (Scalable Vector Extension)
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- FEAT_SVE_AES (Scalable Vector AES instructions)
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- FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2)
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+- FEAT_SVE_BFSCALE (BFloat16 Floating-Point Adjust Exponent)
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- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
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- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
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- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
linux-user/aarch64/elfload.c
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@@ -180,6 +180,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_sme_tmop, ARM_HWCAP_A64_SME_STMOP);
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GET_FEATURE_ID(aa64_sve2p2, ARM_HWCAP_A64_SVE2P2);
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GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2);
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+ GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
+1
-1
@@ -1474,7 +1474,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMULL128 */
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t = FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */
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t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitPerm */
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- t = FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B16 */
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+ t = FIELD_DP64(t, ID_AA64ZFR0, B16B16, 2); /* v9.2: FEAT_SVE_BFSCALE */
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t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3 */
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t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 */
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SET_IDREG(isar, ID_AA64ZFR0, t);