target/riscv: move csr.h to tcg subdir
After KVM is no longer reliant on csr.h move it to the TGC only land. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703180538.3346781-11-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 3, 2026 at 15:05 UTC
458630c430232010b4a265bfde926697182c9134
10 files changed
+9
-9
target/riscv/cpu.c
+1
-1
@@ -24,7 +24,7 @@
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#include "qemu/guest-random.h"
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#include "cpu.h"
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#include "cpu_vendorid.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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#include "internals.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
target/riscv/gdbstub.c
+1
-1
@@ -21,7 +21,7 @@
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#include "gdbstub/helpers.h"
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#include "cpu.h"
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#include "internals.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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struct TypeSize {
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const char *gdb_type;
target/riscv/monitor.c
+1
-1
@@ -22,7 +22,7 @@
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#include "qemu/ctype.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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#include "cpu_bits.h"
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#include "monitor/monitor.h"
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#include "monitor/hmp.h"
target/riscv/riscv-qmp-cmds.c
+1
-1
@@ -35,7 +35,7 @@
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#include "system/tcg.h"
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#include "cpu-qom.h"
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#include "cpu.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
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{
target/riscv/tcg/csr.c
+1
-1
@@ -21,7 +21,7 @@
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "cpu.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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#include "tcg/tcg-cpu.h"
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#include "pmu.h"
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#include "time_helper.h"
target/riscv/tcg/csr.h
renamed
target/riscv/tcg/mips_csr.c
+1
-1
@@ -10,7 +10,7 @@
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu_vendorid.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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/* Static MIPS CSR state storage */
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static struct {
target/riscv/tcg/op_helper.c
+1
-1
@@ -20,7 +20,7 @@
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#include "qemu/osdep.h"
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#include "cpu.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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#include "internals.h"
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#include "exec/cputlb.h"
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#include "accel/tcg/cpu-ldst.h"
target/riscv/tcg/pmp.c
+1
-1
@@ -23,7 +23,7 @@
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "cpu.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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#include "trace.h"
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#include "exec/cputlb.h"
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#include "exec/page-protection.h"
target/riscv/tcg/th_csr.c
+1
-1
@@ -22,7 +22,7 @@
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu_vendorid.h"
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-#include "target/riscv/csr.h"
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+#include "target/riscv/tcg/csr.h"
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/* Extended M-mode control registers of T-Head */
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#define CSR_TH_MXSTATUS 0x7c0