hw/dma/omap_dma: Fold omap_dma_sys_read() and omap_dma_sys_write() into callers
Now we have removed the DMA 3.2 support, we call omap_dma_sys_read() only for the single address offset 0x400, and similarly for omap_dma_sys_write(). The other cases in those functions are DMA 3.2-only and now dead code. Fold the 0x400 register directly into the callers, and remove the rest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260512203414.3633237-9-peter.maydell@linaro.org
Peter Maydell committed
May 12, 2026 at 21:34 UTC
46c7953e9adff0cd09d2f1f5d736d9d60bcaee9e
1 file changed
+5
-116
hw/dma/omap_dma.c
+5
-116
@@ -317,16 +317,6 @@ static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
317
qemu_irq_raise(ch[5].irq);
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}
319
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-static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
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-{
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- struct omap_dma_channel_s *ch = s->ch;
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- int i;
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-
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- for (i = s->chans; i; ch ++, i --)
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- if (ch->status)
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- qemu_irq_raise(ch->irq);
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-}
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-
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static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
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{
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s->omap_3_1_mapping_disabled = 0;
@@ -334,13 +324,6 @@ static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
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s->intr_update = omap_dma_interrupts_3_1_update;
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}
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-static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
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-{
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- s->omap_3_1_mapping_disabled = 1;
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- s->chans = 16;
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- s->intr_update = omap_dma_interrupts_3_2_update;
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-}
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-
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static void omap_dma_process_request(struct omap_dma_s *s, int request)
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{
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int channel;
@@ -1106,98 +1089,6 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
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return 0;
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}
1091
1109
-static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1110
-{
1111
- switch (offset) {
1112
- case 0x400: /* SYS_DMA_GCR */
1113
- s->gcr = value;
1114
- break;
1115
-
1116
- case 0x404: /* DMA_GSCR */
1117
- if (value & 0x8)
1118
- omap_dma_disable_3_1_mapping(s);
1119
- else
1120
- omap_dma_enable_3_1_mapping(s);
1121
- break;
1122
-
1123
- case 0x408: /* DMA_GRST */
1124
- if (value & 0x1)
1125
- omap_dma_reset(s->dma);
1126
- break;
1127
-
1128
- default:
1129
- return 1;
1130
- }
1131
- return 0;
1132
-}
1133
-
1134
-static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
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- uint16_t *ret)
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-{
1137
- switch (offset) {
1138
- case 0x400: /* SYS_DMA_GCR */
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- *ret = s->gcr;
1140
- break;
1141
-
1142
- case 0x404: /* DMA_GSCR */
1143
- *ret = s->omap_3_1_mapping_disabled << 3;
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- break;
1145
-
1146
- case 0x408: /* DMA_GRST */
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- *ret = 0;
1148
- break;
1149
-
1150
- case 0x442: /* DMA_HW_ID */
1151
- case 0x444: /* DMA_PCh2_ID */
1152
- case 0x446: /* DMA_PCh0_ID */
1153
- case 0x448: /* DMA_PCh1_ID */
1154
- case 0x44a: /* DMA_PChG_ID */
1155
- case 0x44c: /* DMA_PChD_ID */
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- *ret = 1;
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- break;
1158
-
1159
- case 0x44e: /* DMA_CAPS_0_U */
1160
- *ret = (s->caps[0] >> 16) & 0xffff;
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- break;
1162
- case 0x450: /* DMA_CAPS_0_L */
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- *ret = (s->caps[0] >> 0) & 0xffff;
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- break;
1165
-
1166
- case 0x452: /* DMA_CAPS_1_U */
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- *ret = (s->caps[1] >> 16) & 0xffff;
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- break;
1169
- case 0x454: /* DMA_CAPS_1_L */
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- *ret = (s->caps[1] >> 0) & 0xffff;
1171
- break;
1172
-
1173
- case 0x456: /* DMA_CAPS_2 */
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- *ret = s->caps[2];
1175
- break;
1176
-
1177
- case 0x458: /* DMA_CAPS_3 */
1178
- *ret = s->caps[3];
1179
- break;
1180
-
1181
- case 0x45a: /* DMA_CAPS_4 */
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- *ret = s->caps[4];
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- break;
1184
-
1185
- case 0x460: /* DMA_PCh2_SR */
1186
- case 0x480: /* DMA_PCh0_SR */
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- case 0x482: /* DMA_PCh1_SR */
1188
- case 0x4c0: /* DMA_PChD_SR_0 */
1189
- qemu_log_mask(LOG_UNIMP,
1190
- "%s: Physical Channel Status Registers not implemented\n",
1191
- __func__);
1192
- *ret = 0xff;
1193
- break;
1194
-
1195
- default:
1196
- return 1;
1197
- }
1198
- return 0;
1199
-}
1200
-
1092
static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
1093
{
1094
struct omap_dma_s *s = opaque;
@@ -1225,10 +1116,9 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
1116
1117
case 0x404 ... 0x4fe:
1118
break;
1228
- case 0x400:
1229
- if (omap_dma_sys_read(s, addr, &ret))
1230
- break;
1231
- return ret;
1119
+ case 0x400: /* SYS_DMA_GCR */
1120
+ return s->gcr;
1121
+ break;
1122
1123
case 0xb00 ... 0xbfe:
1124
break;
@@ -1265,9 +1155,8 @@ static void omap_dma_write(void *opaque, hwaddr addr,
1155
1156
case 0x404 ... 0x4fe:
1157
break;
1268
- case 0x400:
1269
- if (omap_dma_sys_write(s, addr, value))
1270
- break;
1158
+ case 0x400: /* SYS_DMA_GCR */
1159
+ s->gcr = value;
1160
return;
1161
1162
case 0xb00 ... 0xbfe: