hw/block: m25p80: Fix dummy byte handling for Spansion flash
Spansion flashes expose the number of dummy clock cycles through CR2V register [1]. The value is a cycle count, not a byte count, so the m25p80 model has to convert it to the number of whole SSI transfer bytes consumed while collecting read command data. Add a helper that multiplies the CR2V dummy cycle count by the phase width and rounds up non-byte-aligned counts, matching the byte-oriented SSI model. The default eight-cycle configuration keeps the same byte counts as before. [1] https://www.infineon.com/assets/row/public/documents/10/49/infineon-s25fs128s-s25fs256s-1-datasheet-en.pdf Fixes: cf6f1efe0b57 ("m25p80: Fast read commands family changes") Signed-off-by: Bin Meng <bin.meng@processmission.com> Tested-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20260707083431.219671-5-bin.meng@processmission.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>