target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207
There are several flags for Power ISA 2.07 currently in use, namely : PPC2_VSX207, PPC2_BCTAR_ISA207, PPC2_LSQ_ISA207, etc, but most of them are used together without any individual use. Create a generic ISA 2.07 flag and switch usage of PPC2_VSX207 to it instead. Next commits would consolidate the remaining flags. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-31-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Chinmay Rath committed
Aug 27, 2026 at 18:59 UTC
4a1712f43e697486fee56ca767737ad08bffa5b2
6 files changed
+47
-47
target/ppc/cpu.h
+3
-3
@@ -2565,8 +2565,8 @@ enum {
2565
PPC2_DBRX = 0x0000000000000010ULL,
2566
/* Book I 2.05 PowerPC specification */
2567
PPC2_ISA205 = 0x0000000000000020ULL,
2568
- /* VSX additions in ISA 2.07 */
2569
- PPC2_VSX207 = 0x0000000000000040ULL,
2568
+ /* POWER ISA 2.07 */
2569
+ PPC2_ISA207 = 0x0000000000000040ULL,
2570
/* ISA 2.06B bpermd */
2571
PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2572
/* ISA 2.06B divide extended variants */
@@ -2607,7 +2607,7 @@ enum {
2607
PPC2_PPE42XM = 0x0000000002000000ULL,
2608
2609
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2610
- PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2610
+ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
2611
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2612
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2613
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
target/ppc/cpu_init.c
+1
-1
@@ -6346,7 +6346,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
6346
PPC_SEGMENT_64B | PPC_SLBI |
6347
PPC_POPCNTB | PPC_POPCNTWD |
6348
PPC_CILDST;
6349
- pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6349
+ pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
6350
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6351
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6352
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
target/ppc/cpu_init.h
+1
-1
@@ -15,7 +15,7 @@
15
#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10
16
17
#define PPC_INSNS_FLAGS2_POWER_COMMON \
18
- (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \
18
+ (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \
19
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
20
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \
21
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \
target/ppc/translate/fp-impl.c.inc
+2
-2
@@ -342,7 +342,7 @@ static bool trans_FCPSGN(DisasContext *ctx, arg_FCPSGN *a)
342
static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW *a)
343
{
344
TCGv_i64 t0, t1, t2;
345
- REQUIRE_INSNS_FLAGS2(ctx, VSX207);
345
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
346
REQUIRE_FPU(ctx);
347
t0 = tcg_temp_new_i64();
348
t1 = tcg_temp_new_i64();
@@ -358,7 +358,7 @@ static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW *a)
358
static bool trans_FMRGOW(DisasContext *ctx, arg_FMRGOW *a)
359
{
360
TCGv_i64 t0, t1, t2;
361
- REQUIRE_INSNS_FLAGS2(ctx, VSX207);
361
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
362
REQUIRE_FPU(ctx);
363
t0 = tcg_temp_new_i64();
364
t1 = tcg_temp_new_i64();
target/ppc/translate/vsx-impl.c.inc
+28
-28
@@ -50,11 +50,11 @@ static bool do_lxs(DisasContext *ctx, arg_X *a,
50
}
51
52
TRANS_FLAGS2(VSX, LXSDX, do_lxs, gen_qemu_ld64_i64);
53
-TRANS_FLAGS2(VSX207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64);
53
+TRANS_FLAGS2(ISA207, LXSIWAX, do_lxs, gen_qemu_ld32s_i64);
54
TRANS_FLAGS2(ISA300, LXSIBZX, do_lxs, gen_qemu_ld8u_i64);
55
TRANS_FLAGS2(ISA300, LXSIHZX, do_lxs, gen_qemu_ld16u_i64);
56
-TRANS_FLAGS2(VSX207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64);
57
-TRANS_FLAGS2(VSX207, LXSSPX, do_lxs, gen_qemu_ld32fs);
56
+TRANS_FLAGS2(ISA207, LXSIWZX, do_lxs, gen_qemu_ld32u_i64);
57
+TRANS_FLAGS2(ISA207, LXSSPX, do_lxs, gen_qemu_ld32fs);
58
59
static bool trans_LXVD2X(DisasContext *ctx, arg_LXVD2X *a)
60
{
@@ -304,8 +304,8 @@ static bool do_stxs(DisasContext *ctx, arg_X *a,
304
TRANS_FLAGS2(VSX, STXSDX, do_stxs, gen_qemu_st64_i64);
305
TRANS_FLAGS2(ISA300, STXSIBX, do_stxs, gen_qemu_st8_i64);
306
TRANS_FLAGS2(ISA300, STXSIHX, do_stxs, gen_qemu_st16_i64);
307
-TRANS_FLAGS2(VSX207, STXSIWX, do_stxs, gen_qemu_st32_i64);
308
-TRANS_FLAGS2(VSX207, STXSSPX, do_stxs, gen_qemu_st32fs);
307
+TRANS_FLAGS2(ISA207, STXSIWX, do_stxs, gen_qemu_st32_i64);
308
+TRANS_FLAGS2(ISA207, STXSSPX, do_stxs, gen_qemu_st32fs);
309
310
static bool trans_STXVD2X(DisasContext *ctx, arg_STXVD2X *a)
311
{
@@ -988,7 +988,7 @@ GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
988
GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
989
GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
990
GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
991
-GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
991
+GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_ISA207)
992
GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
993
GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
994
GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300)
@@ -1185,7 +1185,7 @@ bool trans_XSCVSPDPN(DisasContext *ctx, arg_XX2 *a)
1185
{
1186
TCGv_i64 tmp;
1187
1188
- REQUIRE_INSNS_FLAGS2(ctx, VSX207);
1188
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
1189
REQUIRE_VSX(ctx);
1190
1191
tmp = tcg_temp_new_i64();
@@ -1210,16 +1210,16 @@ GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
1210
GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
1211
GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
1212
GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
1213
-GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
1213
+GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_ISA207)
1214
GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
1215
GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
1216
GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
1217
GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300)
1218
-GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
1219
-GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
1220
-GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
1221
-GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
1222
-GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
1218
+GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_ISA207)
1219
+GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_ISA207)
1220
+GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_ISA207)
1221
+GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_ISA207)
1222
+GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_ISA207)
1223
1224
GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
1225
GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
@@ -1409,14 +1409,14 @@ TRANS_FLAGS2(VSX, XSNMADDADP, do_xsmadd_XX3, true, gen_helper_XSNMADDDP)
1409
TRANS_FLAGS2(VSX, XSNMADDMDP, do_xsmadd_XX3, false, gen_helper_XSNMADDDP)
1410
TRANS_FLAGS2(VSX, XSNMSUBADP, do_xsmadd_XX3, true, gen_helper_XSNMSUBDP)
1411
TRANS_FLAGS2(VSX, XSNMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSNMSUBDP)
1412
-TRANS_FLAGS2(VSX207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP)
1413
-TRANS_FLAGS2(VSX207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP)
1414
-TRANS_FLAGS2(VSX207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP)
1415
-TRANS_FLAGS2(VSX207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP)
1416
-TRANS_FLAGS2(VSX207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP)
1417
-TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
1418
-TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
1419
-TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
1412
+TRANS_FLAGS2(ISA207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP)
1413
+TRANS_FLAGS2(ISA207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP)
1414
+TRANS_FLAGS2(ISA207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP)
1415
+TRANS_FLAGS2(ISA207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP)
1416
+TRANS_FLAGS2(ISA207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP)
1417
+TRANS_FLAGS2(ISA207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
1418
+TRANS_FLAGS2(ISA207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
1419
+TRANS_FLAGS2(ISA207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
1420
1421
static bool do_xsmadd_X(DisasContext *ctx, arg_X_rc *a,
1422
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr),
@@ -1590,9 +1590,9 @@ TRANS_FLAGS2(VSX, XXLANDC, do_logical_op, MO_64, tcg_gen_gvec_andc);
1590
TRANS_FLAGS2(VSX, XXLOR, do_logical_op, MO_64, tcg_gen_gvec_or);
1591
TRANS_FLAGS2(VSX, XXLXOR, do_logical_op, MO_64, tcg_gen_gvec_xor);
1592
TRANS_FLAGS2(VSX, XXLNOR, do_logical_op, MO_64, tcg_gen_gvec_nor);
1593
-TRANS_FLAGS2(VSX207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv);
1594
-TRANS_FLAGS2(VSX207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand);
1595
-TRANS_FLAGS2(VSX207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc);
1593
+TRANS_FLAGS2(ISA207, XXLEQV, do_logical_op, MO_64, tcg_gen_gvec_eqv);
1594
+TRANS_FLAGS2(ISA207, XXLNAND, do_logical_op, MO_64, tcg_gen_gvec_nand);
1595
+TRANS_FLAGS2(ISA207, XXLORC, do_logical_op, MO_64, tcg_gen_gvec_orc);
1596
1597
#define VSX_XXMRG(name, high) \
1598
static void glue(gen_, name)(DisasContext *ctx) \
@@ -2682,10 +2682,10 @@ TRANS_FLAGS2(ISA300, XSMINCDP, do_helper_XX3, gen_helper_XSMINCDP)
2682
TRANS_FLAGS2(ISA300, XSMAXJDP, do_helper_XX3, gen_helper_XSMAXJDP)
2683
TRANS_FLAGS2(ISA300, XSMINJDP, do_helper_XX3, gen_helper_XSMINJDP)
2684
2685
-TRANS_FLAGS2(VSX207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP)
2686
-TRANS_FLAGS2(VSX207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP)
2687
-TRANS_FLAGS2(VSX207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP)
2688
-TRANS_FLAGS2(VSX207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP)
2685
+TRANS_FLAGS2(ISA207, XSADDSP, do_helper_XX3, gen_helper_XSADDSP)
2686
+TRANS_FLAGS2(ISA207, XSSUBSP, do_helper_XX3, gen_helper_XSSUBSP)
2687
+TRANS_FLAGS2(ISA207, XSMULSP, do_helper_XX3, gen_helper_XSMULSP)
2688
+TRANS_FLAGS2(ISA207, XSDIVSP, do_helper_XX3, gen_helper_XSDIVSP)
2689
2690
TRANS_FLAGS2(VSX, XSADDDP, do_helper_XX3, gen_helper_XSADDDP)
2691
TRANS_FLAGS2(VSX, XSSUBDP, do_helper_XX3, gen_helper_XSSUBDP)
target/ppc/translate/vsx-ops.c.inc
+12
-12
@@ -1,9 +1,9 @@
1
-GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2
-GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3
-GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
1
+GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_ISA207),
2
+GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_ISA207),
3
+GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_ISA207),
4
#if defined(TARGET_PPC64)
5
-GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6
-GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
5
+GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_ISA207),
6
+GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_ISA207),
7
GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8
GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9
GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
@@ -127,7 +127,7 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
127
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
128
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
129
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
130
-GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
130
+GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_ISA207),
131
GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
132
GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001),
133
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
@@ -145,12 +145,12 @@ GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
145
GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
146
147
GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0),
148
-GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
149
-GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
150
-GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
151
-GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
152
-GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
153
-GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
148
+GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_ISA207),
149
+GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_ISA207),
150
+GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_ISA207),
151
+GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_ISA207),
152
+GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_ISA207),
153
+GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_ISA207),
154
155
GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
156
GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),