target/loongarch: Add macro CSR_OFFSET and CPU_CSR_OFFSET
Instruction rdtime is to read TSC timestamp and logic vCPU id, it is also used by Linux user mode emulation. However function get_csr_offset() cannot be called in user mode emulation, here macro CSR_OFFSET and CPU_CSR_OFFSET are added. The added macro can be called in both user emulation and system emulation. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Tested-by: Song Gao <gaosong@loongson.cn> Message-ID: <20260605083910.175647-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Bibo Mao committed
Jun 5, 2026 at 16:39 UTC
4a5d2c649dabee3d1cbfd2e91353e5a94576a871
3 files changed
+10
-3
target/loongarch/csr.c
+2
-2
@@ -9,14 +9,14 @@
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#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \
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[LOONGARCH_CSR_##NAME] = { \
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.name = (stringify(NAME)), \
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- .offset = offsetof(CPULoongArchState, CSR_##NAME), \
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+ .offset = CSR_OFFSET(CSR_##NAME), \
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.flags = FL, .readfn = RD, .writefn = WR \
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}
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#define CSR_OFF_ARRAY(NAME, N) \
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[LOONGARCH_CSR_##NAME(N)] = { \
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.name = (stringify(NAME##N)), \
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- .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
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+ .offset = CSR_OFFSET(CSR_##NAME[N]), \
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.flags = CSRFL_BASIC, .readfn = NULL, .writefn = NULL \
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}
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target/loongarch/csr.h
+3
@@ -8,6 +8,9 @@
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#include "cpu-csr.h"
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+#define CSR_OFFSET(id) offsetof(CPULoongArchState, id)
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+#define CPU_CSR_OFFSET(id, vm_level) CSR_OFFSET(id)
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+
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typedef void (*GenCSRFunc)(void);
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enum {
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CSRFL_READONLY = (1 << 0),
target/loongarch/tcg/insn_trans/trans_extra.c.inc
+5
-1
@@ -3,6 +3,7 @@
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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+#include "csr.h"
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static bool trans_break(DisasContext *ctx, arg_break *a)
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{
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generate_exception(ctx, EXCCODE_BRK);
@@ -46,13 +47,16 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
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{
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TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
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+ tcg_target_long offset;
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translator_io_start(&ctx->base);
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gen_helper_rdtime_d(dst1, tcg_env);
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if (word) {
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tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
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}
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- tcg_gen_ld_i64(dst2, tcg_env, offsetof(CPULoongArchState, CSR_TID));
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+
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+ offset = CPU_CSR_OFFSET(CSR_TID, 0);
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+ tcg_gen_ld_i64(dst2, tcg_env, offset);
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return true;
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}