@samitouri / QOSamiQemu / commits / 4a884ba94b

target/riscv: Fix PC sync in trans_sspopchk for CFI exception handling

Move gen_update_pc call before conditional logic to ensure consistent PC state regardless of execution path. Previously, the host instructions generated to update the cpu_pc were only executed in the failure path when shadow stack validation failed. This created inconsistent PC synchronization. This inconsistency caused issues in CF_PCREL mode where subsequent instructions calculated wrong relative offsets from stale pc_save values, and could lead to incorrect exception return addresses. This fix ensures PC is always synchronized before any helper that might raise an exception, maintaining consistent translator state across all execution paths. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/4118 Signed-off-by: Max Chou <max.chou@sifive.com> [ahshehab: rebased on current master; file moved to target/riscv/tcg/insn_trans/ and the ssp load is now 64-bit wide] Tested-by: A-Shehab <ahshehab24@gmail.com> Signed-off-by: A-Shehab <ahshehab24@gmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260730181852.1622-1-ahshehab24@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Max Chou committed Jul 30, 2026 at 21:18 UTC 4a884ba94b43f5b2a640f4ea882655503f9ae954

1 file changed +1 -1

target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc

+1 -1

@@ -32,6 +32,7 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)

32 TCGLabel *skip = gen_new_label();

33 uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4;

34 TCGv data = tcg_temp_new();

35 + gen_update_pc(ctx, 0);

36 TCGv_i64 wide_addr = tcg_temp_new_i64();

37 tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));

38 tcg_gen_trunc_i64_tl(addr, wide_addr);

@@ -42,7 +43,6 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)

43 tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip);

44 tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_BCFI_TVAL),

45 tcg_env, offsetof(CPURISCVState, sw_check_code));

45 - gen_update_pc(ctx, 0);

46 gen_helper_raise_exception(tcg_env,

47 tcg_constant_i32(RISCV_EXCP_SW_CHECK));

48 gen_set_label(skip);