target/arm/tcg/cpu-v7m.c: add cortex-m85 model
Add Arm Cortex-M85 CPU. This is quite similar to the existing Cortex-M85. ID register values are based on the r1p1 TRM: https://developer.arm.com/documentation/101924/0101/ In hardware, PACBTI support can be configured in or out; as QEMU does not yet implement it, we report it as not present in ID_ISAR5. Reviewed-by: Owen Giles <owen.giles@hpe.com> Reviewed-by: Robert Elliott <elliott@hpe.com> Signed-off-by: Simon Xu <simonxhy0404@gmail.com> Message-Id: <20260805153005.9989-2-simonxhy0404@gmail.com> [PMM: tweaked commit message, expanded comment about PACBTI] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Simon Xu committed
Aug 17, 2026 at 19:26 UTC
4b5309cd1f20eab1dd243dafb6b0b1b1f80dc1f6
1 file changed
+47
target/arm/tcg/cpu-v7m.c
+47
@@ -237,6 +237,51 @@ static void cortex_m55_initfn(Object *obj)
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cpu->ctr = 0x8303c003;
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}
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+static void cortex_m85_initfn(Object *obj)
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+{
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+ ARMCPU *cpu = ARM_CPU(obj);
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+ ARMISARegisters *isar = &cpu->isar;
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+
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+ set_feature(&cpu->env, ARM_FEATURE_V8);
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+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
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+ set_feature(&cpu->env, ARM_FEATURE_M);
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+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
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+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
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+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
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+ cpu->midr = 0x411fd231; /* r1p1 */
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+ cpu->revidr = 0;
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+ cpu->pmsav7_dregion = 16;
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+ cpu->sau_sregion = 8;
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+ /* These are the MVFR* values for the FPU + full MVE configuration */
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+ cpu->isar.mvfr0 = 0x10110221;
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+ cpu->isar.mvfr1 = 0x12100211;
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+ cpu->isar.mvfr2 = 0x00000040;
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+ SET_IDREG(isar, ID_PFR0, 0x20000030);
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+ SET_IDREG(isar, ID_PFR1, 0x00000230);
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+ SET_IDREG(isar, ID_DFR0, 0x10200000);
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+ SET_IDREG(isar, ID_AFR0, 0x00000000);
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+ SET_IDREG(isar, ID_MMFR0, 0x00111040);
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+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
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+ SET_IDREG(isar, ID_MMFR2, 0x01000000);
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+ SET_IDREG(isar, ID_MMFR3, 0x00000011);
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+ SET_IDREG(isar, ID_ISAR0, 0x01103110);
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+ SET_IDREG(isar, ID_ISAR1, 0x02212000);
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+ SET_IDREG(isar, ID_ISAR2, 0x20232232);
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+ SET_IDREG(isar, ID_ISAR3, 0x01111131);
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+ SET_IDREG(isar, ID_ISAR4, 0x01310132);
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+ /*
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+ * Real Cortex-M85 CPUs can be configured with or without PACBTI.
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+ * If PACBTI is present then ID_ISAR5[23:20] read as 0b0100,
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+ * indicating that QARMA3 is used. QEMU does not yet implement
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+ * PACBTI emulation for M-profile, so we report as a "no-PACBTI"
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+ * CPU for now.
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+ */
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+ SET_IDREG(isar, ID_ISAR5, 0x00000000);
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+ SET_IDREG(isar, ID_ISAR6, 0x00000000);
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+ SET_IDREG(isar, CLIDR, 0x00000000); /* caches not implemented */
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+ cpu->ctr = 0x8303c003;
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+}
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+
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static const TCGCPUOps arm_v7m_tcg_ops = {
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/* ARM processors have a weak memory model */
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.guest_default_memory_order = 0,
@@ -290,6 +335,8 @@ static const ARMCPUInfo arm_v7m_cpus[] = {
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-m55", .initfn = cortex_m55_initfn,
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.class_init = arm_v7m_class_init },
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+ { .name = "cortex-m85", .initfn = cortex_m85_initfn,
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+ .class_init = arm_v7m_class_init },
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};
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static void arm_v7m_cpu_register_types(void)