target/arm: Implement FEAT_SSVE_AES
Enable FEAT_SVE_AES instructions in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260618040718.572950-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 17, 2026 at 21:07 UTC
4bdbb202406b7110d796f53a8220c5b5400282fd
5 files changed
+20
-10
docs/system/arm/emulation.rst
+1
@@ -171,6 +171,7 @@ the following architecture extensions:
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- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
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- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
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- FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements)
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+- FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-bit polynomial multiply long instructions)
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- FEAT_SSVE_FP8DOT2 (SVE2 FP8 2-way dot product to half-precision instructions in Streaming SVE mode)
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- FEAT_SSVE_FP8DOT4 (SVE2 FP8 4-way dot product to single-precision instructions in Streaming SVE mode)
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- FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode)
linux-user/aarch64/elfload.c
+1
@@ -173,6 +173,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_cmpbr, ARM_HWCAP_A64_CMPBR);
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GET_FEATURE_ID(aa64_f8mm8, ARM_HWCAP_A64_F8MM8);
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GET_FEATURE_ID(aa64_f8mm4, ARM_HWCAP_A64_F8MM4);
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+ GET_FEATURE_ID(aa64_ssve_aes, ARM_HWCAP_A64_SME_AES);
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return hwcaps;
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}
target/arm/cpu-features.h
+5
@@ -1575,6 +1575,11 @@ static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16);
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}
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+static inline bool isar_feature_aa64_ssve_aes(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, AES);
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+}
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+
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static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);
target/arm/tcg/cpu64.c
+1
@@ -1383,6 +1383,7 @@ void aarch64_max_tcg_initfn(Object *obj)
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SET_IDREG(isar, ID_AA64DFR0, t);
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t = GET_IDREG(isar, ID_AA64SMFR0);
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+ t = FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* FEAT_SSVE_AES */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* FEAT_SSVE_FP8DOT2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* FEAT_SSVE_FP8DOT4 */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* FEAT_SSVE_FP8FMA */
target/arm/tcg/translate-sve.c
+12
-10
@@ -7169,7 +7169,7 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
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if (!dc_isar_feature(aa64_sve2_pmull128, s)) {
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return false;
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}
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- s->is_nonstreaming = true;
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+ s->is_nonstreaming = !dc_isar_feature(aa64_ssve_aes, s);
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}
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return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
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}
@@ -8174,15 +8174,17 @@ TRANS_FEAT(SDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz,
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TRANS_FEAT(UDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz,
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gen_helper_gvec_udot_2h, a, 0)
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-TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve_aes, gen_gvec_ool_zz,
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- gen_helper_crypto_aesmc, a->rd, a->rd, 0)
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-TRANS_FEAT_NONSTREAMING(AESIMC, aa64_sve_aes, gen_gvec_ool_zz,
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- gen_helper_crypto_aesimc, a->rd, a->rd, 0)
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-
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-TRANS_FEAT_NONSTREAMING(AESE, aa64_sve_aes, gen_gvec_ool_arg_zzz,
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- gen_helper_crypto_aese, a, 0)
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-TRANS_FEAT_NONSTREAMING(AESD, aa64_sve_aes, gen_gvec_ool_arg_zzz,
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- gen_helper_crypto_aesd, a, 0)
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+TRANS_FEAT_STREAMING_IF(AESMC, aa64_sve_aes, aa64_ssve_aes,
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+ gen_gvec_ool_zz, gen_helper_crypto_aesmc,
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+ a->rd, a->rd, 0)
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+TRANS_FEAT_STREAMING_IF(AESIMC, aa64_sve_aes, aa64_ssve_aes,
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+ gen_gvec_ool_zz, gen_helper_crypto_aesimc,
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+ a->rd, a->rd, 0)
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+
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+TRANS_FEAT_STREAMING_IF(AESE, aa64_sve_aes, aa64_ssve_aes,
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+ gen_gvec_ool_arg_zzz, gen_helper_crypto_aese, a, 0)
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+TRANS_FEAT_STREAMING_IF(AESD, aa64_sve_aes, aa64_ssve_aes,
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+ gen_gvec_ool_arg_zzz, gen_helper_crypto_aesd, a, 0)
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TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
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gen_helper_crypto_sm4e, a, 0)