disas/riscv: Split rvi_opcode_data
Generate separate objects for OP() instead of collecting in a table. Return pointers to objects directly. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-52-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
4fec981f18fd13adc44d2c58ccfd502612f10dc8
2 files changed
+1048
-1027
disas/riscv-op.c.inc
+47
-47
@@ -225,51 +225,51 @@ OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
225
OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
226
OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
227
OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
228
-OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(rv_op_addi))
229
-OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld))
230
-OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw))
231
-OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw))
232
-OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd))
233
-OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw))
234
-OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw))
235
-OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi))
236
-OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal))
237
-OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi))
238
-OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(rv_op_addi))
239
-OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui))
240
-OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli))
241
-OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai))
242
-OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi))
243
-OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub))
244
-OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor))
245
-OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or))
246
-OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and))
247
-OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw))
248
-OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw))
249
-OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j))
250
-OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz))
251
-OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez))
252
-OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli))
253
-OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld))
254
-OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw))
255
-OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw))
256
-OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr))
257
-OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv))
258
-OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak))
259
-OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr))
260
-OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add))
261
-OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd))
262
-OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw))
263
-OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw))
264
-OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld))
265
-OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd))
266
-OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw))
267
-OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld))
268
-OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd))
269
-OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq))
270
-OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq))
271
-OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq))
272
-OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq))
228
+OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(op_addi))
229
+OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
230
+OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
231
+OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
232
+OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
233
+OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
234
+OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
235
+OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
236
+OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
237
+OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
238
+OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(op_addi))
239
+OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
240
+OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
241
+OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
242
+OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
243
+OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
244
+OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
245
+OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
246
+OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
247
+OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
248
+OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
249
+OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
250
+OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
251
+OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
252
+OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
253
+OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
254
+OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
255
+OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
256
+OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
257
+OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
258
+OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
259
+OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
260
+OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
261
+OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
262
+OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
263
+OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
264
+OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
265
+OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
266
+OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
267
+OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
268
+OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
269
+OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
270
+OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
271
+OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
272
+OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
273
OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
274
OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
275
OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
@@ -904,8 +904,8 @@ OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
904
OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
905
OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
906
OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
907
-OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspush))
908
-OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspopchk))
907
+OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
908
+OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(op_sspopchk))
909
OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
910
OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
911
OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
disas/riscv.c
+1001
-980
@@ -28,12 +28,6 @@
28
#include "disas/riscv-xventana.h"
29
#include "disas/riscv-xlrbr.h"
30
31
-typedef enum {
32
-#define OP(N, ...) rv_op_##N,
33
-#include "riscv-op.c.inc"
34
-#undef OP
35
-} rv_op;
36
-
31
/* register names */
32
33
static const char rv_ireg_name_sym[32][5] = {
@@ -113,140 +107,143 @@ static const rvc_constraint rvcc_true[] = { rvc_end };
107
108
/* pseudo-instruction metadata */
109
116
-static const rv_opcode_data rvi_opcode_data[];
110
+/* Forward declare the all the opcodes so that we may link them. */
111
+#define OP(N, ...) static const rv_opcode_data op_##N;
112
+#include "riscv-op.c.inc"
113
+#undef OP
114
115
static const rv_comp_data rvcp_jal[] = {
119
- { &rvi_opcode_data[rv_op_j], rvcc_j },
120
- { &rvi_opcode_data[rv_op_jal_ra], rvcc_jal_ra },
116
+ { &op_j, rvcc_j },
117
+ { &op_jal_ra, rvcc_jal_ra },
118
{ },
119
};
120
121
static const rv_comp_data rvcp_jalr[] = {
125
- { &rvi_opcode_data[rv_op_jr], rvcc_jr },
126
- { &rvi_opcode_data[rv_op_jalr_ra], rvcc_jalr_ra },
122
+ { &op_jr, rvcc_jr },
123
+ { &op_jalr_ra, rvcc_jalr_ra },
124
{ },
125
};
126
127
static const rv_comp_data rvcp_jr[] = {
131
- { &rvi_opcode_data[rv_op_ret], rvcc_ret },
128
+ { &op_ret, rvcc_ret },
129
{ },
130
};
131
132
static const rv_comp_data rvcp_beq[] = {
136
- { &rvi_opcode_data[rv_op_beqz], rvcc_beqz },
133
+ { &op_beqz, rvcc_beqz },
134
{ },
135
};
136
137
static const rv_comp_data rvcp_bne[] = {
141
- { &rvi_opcode_data[rv_op_bnez], rvcc_bnez },
138
+ { &op_bnez, rvcc_bnez },
139
{ },
140
};
141
142
static const rv_comp_data rvcp_blt[] = {
146
- { &rvi_opcode_data[rv_op_bltz], rvcc_bltz },
147
- { &rvi_opcode_data[rv_op_bgtz], rvcc_bgtz },
143
+ { &op_bltz, rvcc_bltz },
144
+ { &op_bgtz, rvcc_bgtz },
145
{ },
146
};
147
148
static const rv_comp_data rvcp_bge[] = {
152
- { &rvi_opcode_data[rv_op_blez], rvcc_blez },
153
- { &rvi_opcode_data[rv_op_bgez], rvcc_bgez },
149
+ { &op_blez, rvcc_blez },
150
+ { &op_bgez, rvcc_bgez },
151
{ },
152
};
153
154
static const rv_comp_data rvcp_addi[] = {
158
- { &rvi_opcode_data[rv_op_mv], rvcc_mv },
155
+ { &op_mv, rvcc_mv },
156
{ },
157
};
158
159
static const rv_comp_data rvcp_mv[] = {
163
- { &rvi_opcode_data[rv_op_nop], rvcc_nop },
160
+ { &op_nop, rvcc_nop },
161
{ },
162
};
163
164
static const rv_comp_data rvcp_sltiu[] = {
168
- { &rvi_opcode_data[rv_op_seqz], rvcc_seqz },
165
+ { &op_seqz, rvcc_seqz },
166
{ },
167
};
168
169
static const rv_comp_data rvcp_xori[] = {
173
- { &rvi_opcode_data[rv_op_not], rvcc_not },
170
+ { &op_not, rvcc_not },
171
{ },
172
};
173
174
static const rv_comp_data rvcp_sub[] = {
178
- { &rvi_opcode_data[rv_op_neg], rvcc_neg },
175
+ { &op_neg, rvcc_neg },
176
{ },
177
};
178
179
static const rv_comp_data rvcp_slt[] = {
183
- { &rvi_opcode_data[rv_op_sltz], rvcc_sltz },
184
- { &rvi_opcode_data[rv_op_sgtz], rvcc_sgtz },
180
+ { &op_sltz, rvcc_sltz },
181
+ { &op_sgtz, rvcc_sgtz },
182
{ },
183
};
184
185
static const rv_comp_data rvcp_sltu[] = {
189
- { &rvi_opcode_data[rv_op_snez], rvcc_snez },
186
+ { &op_snez, rvcc_snez },
187
{ },
188
};
189
190
static const rv_comp_data rvcp_addiw[] = {
194
- { &rvi_opcode_data[rv_op_sext_w], rvcc_sext_w },
191
+ { &op_sext_w, rvcc_sext_w },
192
{ },
193
};
194
195
static const rv_comp_data rvcp_subw[] = {
199
- { &rvi_opcode_data[rv_op_negw], rvcc_negw },
196
+ { &op_negw, rvcc_negw },
197
{ },
198
};
199
200
static const rv_comp_data rvcp_fsgnj_s[] = {
204
- { &rvi_opcode_data[rv_op_fmv_s], rvcc_fmv_s },
201
+ { &op_fmv_s, rvcc_fmv_s },
202
{ },
203
};
204
205
static const rv_comp_data rvcp_fsgnjn_s[] = {
209
- { &rvi_opcode_data[rv_op_fneg_s], rvcc_fneg_s },
206
+ { &op_fneg_s, rvcc_fneg_s },
207
{ },
208
};
209
210
static const rv_comp_data rvcp_fsgnjx_s[] = {
214
- { &rvi_opcode_data[rv_op_fabs_s], rvcc_fabs_s },
211
+ { &op_fabs_s, rvcc_fabs_s },
212
{ },
213
};
214
215
static const rv_comp_data rvcp_fsgnj_d[] = {
219
- { &rvi_opcode_data[rv_op_fmv_d], rvcc_fmv_d },
216
+ { &op_fmv_d, rvcc_fmv_d },
217
{ },
218
};
219
220
static const rv_comp_data rvcp_fsgnjn_d[] = {
224
- { &rvi_opcode_data[rv_op_fneg_d], rvcc_fneg_d },
221
+ { &op_fneg_d, rvcc_fneg_d },
222
{ },
223
};
224
225
static const rv_comp_data rvcp_fsgnjx_d[] = {
229
- { &rvi_opcode_data[rv_op_fabs_d], rvcc_fabs_d },
226
+ { &op_fabs_d, rvcc_fabs_d },
227
{ },
228
};
229
230
static const rv_comp_data rvcp_fsgnj_q[] = {
234
- { &rvi_opcode_data[rv_op_fmv_q], rvcc_fmv_q },
231
+ { &op_fmv_q, rvcc_fmv_q },
232
{ },
233
};
234
235
static const rv_comp_data rvcp_fsgnjn_q[] = {
239
- { &rvi_opcode_data[rv_op_fneg_q], rvcc_fneg_q },
236
+ { &op_fneg_q, rvcc_fneg_q },
237
{ },
238
};
239
240
static const rv_comp_data rvcp_fsgnjx_q[] = {
244
- { &rvi_opcode_data[rv_op_fabs_q], rvcc_fabs_q },
241
+ { &op_fabs_q, rvcc_fabs_q },
242
{ },
243
};
244
245
/* Convert compressed insns into normal insns via pseudo expansion. */
249
-#define DECOMP(X) &(const rv_comp_data){ &rvi_opcode_data[X], rvcc_true }
246
+#define DECOMP(X) &(const rv_comp_data){ &X, rvcc_true }
247
248
/* operand extractors */
249
@@ -662,11 +659,9 @@ static uint32_t operand_mop_rr_imm(rv_inst inst)
659
660
/* instruction metadata */
661
665
-static const rv_opcode_data rvi_opcode_data[] = {
666
-#define OP(N, ...) { __VA_ARGS__ },
662
+#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
663
#include "riscv-op.c.inc"
664
#undef OP
669
-};
665
666
/* CSR names */
667
@@ -953,79 +948,65 @@ static const char *csr_name(int csrno)
948
static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
949
{
950
rv_inst inst = dec->inst;
956
- rv_opcode op = rv_op_illegal;
951
952
switch ((inst >> 0) & 0b11) {
953
case 0:
954
switch ((inst >> 13) & 0b111) {
955
case 0:
956
if ((inst >> 5) & 0xff) {
963
- op = rv_op_c_addi4spn;
957
+ return &op_c_addi4spn;
958
}
959
break;
960
case 1:
961
if (isa == rv128) {
968
- op = rv_op_c_lq;
969
- } else {
970
- op = rv_op_c_fld;
962
+ return &op_c_lq;
963
}
972
- break;
973
- case 2: op = rv_op_c_lw; break;
964
+ return &op_c_fld;
965
+ case 2: return &op_c_lw;
966
case 3:
967
if (isa == rv32) {
976
- op = rv_op_c_flw;
977
- } else {
978
- op = rv_op_c_ld;
968
+ return &op_c_flw;
969
}
980
- break;
970
+ return &op_c_ld;
971
case 4:
972
switch ((inst >> 10) & 0b111) {
983
- case 0: op = rv_op_c_lbu; break;
973
+ case 0: return &op_c_lbu;
974
case 1:
975
if (((inst >> 6) & 1) == 0) {
986
- op = rv_op_c_lhu;
987
- } else {
988
- op = rv_op_c_lh;
976
+ return &op_c_lhu;
977
}
990
- break;
991
- case 2: op = rv_op_c_sb; break;
978
+ return &op_c_lh;
979
+ case 2: return &op_c_sb;
980
case 3:
981
if (((inst >> 6) & 1) == 0) {
994
- op = rv_op_c_sh;
982
+ return &op_c_sh;
983
}
984
break;
985
}
986
break;
987
case 5:
988
if (isa == rv128) {
1001
- op = rv_op_c_sq;
1002
- } else {
1003
- op = rv_op_c_fsd;
989
+ return &op_c_sq;
990
}
1005
- break;
1006
- case 6: op = rv_op_c_sw; break;
991
+ return &op_c_fsd;
992
+ case 6: return &op_c_sw;
993
case 7:
994
if (isa == rv32) {
1009
- op = rv_op_c_fsw;
1010
- } else {
1011
- op = rv_op_c_sd;
995
+ return &op_c_fsw;
996
}
1013
- break;
997
+ return &op_c_sd;
998
}
999
break;
1000
case 1:
1001
switch ((inst >> 13) & 0b111) {
1002
case 0:
1019
- op = rv_op_c_addi; /* or unspecified HINT */
1020
- break;
1003
+ return &op_c_addi; /* or unspecified HINT */
1004
case 1:
1005
if (isa == rv32) {
1023
- op = rv_op_c_jal;
1024
- } else {
1025
- op = rv_op_c_addiw;
1006
+ return &op_c_jal;
1007
}
1027
- break;
1028
- case 2: op = rv_op_c_li; break;
1008
+ return &op_c_addiw;
1009
+ case 2: return &op_c_li;
1010
case 3:
1011
if (dec->cfg
1012
&& dec->cfg->ext_zcmop
@@ -1033,16 +1014,16 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
1014
&& ((inst >> 11) & 0b11) == 0) {
1015
if (dec->cfg->ext_zicfiss) {
1016
switch (operand_cmop_imm(inst)) {
1036
- case 1: return &rvi_opcode_data[rv_op_c_sspush];
1037
- case 5: return &rvi_opcode_data[rv_op_c_sspopchk];
1017
+ case 1: return &op_c_sspush;
1018
+ case 5: return &op_c_sspopchk;
1019
}
1020
}
1040
- return &rvi_opcode_data[rv_op_c_mop];
1021
+ return &op_c_mop;
1022
}
1023
if (inst & ((1 << 12) | (0x1f << 2))) {
1024
switch ((inst >> 7) & 0b11111) {
1044
- case 2: op = rv_op_c_addi16sp; break;
1045
- default: op = rv_op_c_lui; break;
1025
+ case 2: return &op_c_addi16sp;
1026
+ default: return &op_c_lui;
1027
}
1028
}
1029
break;
@@ -1051,261 +1032,252 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
1032
case 0:
1033
/* For rv32, shamt[5]=1 is designated for custom extensions. */
1034
if (isa != rv32 || (inst & 0x1000) == 0) {
1054
- op = rv_op_c_srli; /* or unspecified HINT */
1035
+ return &op_c_srli; /* or unspecified HINT */
1036
}
1037
break;
1038
case 1:
1039
/* For rv32, shamt[5]=1 is designated for custom extensions. */
1040
if (isa != rv32 || (inst & 0x1000) == 0) {
1060
- op = rv_op_c_srai; /* or unspecified HINT */
1041
+ return &op_c_srai; /* or unspecified HINT */
1042
}
1043
break;
1063
- case 2: op = rv_op_c_andi; break;
1044
+ case 2: return &op_c_andi;
1045
case 3:
1046
switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
1066
- case 0: op = rv_op_c_sub; break;
1067
- case 1: op = rv_op_c_xor; break;
1068
- case 2: op = rv_op_c_or; break;
1069
- case 3: op = rv_op_c_and; break;
1047
+ case 0: return &op_c_sub;
1048
+ case 1: return &op_c_xor;
1049
+ case 2: return &op_c_or;
1050
+ case 3: return &op_c_and;
1051
case 4:
1052
if (isa != rv32) {
1072
- op = rv_op_c_subw;
1053
+ return &op_c_subw;
1054
}
1055
break;
1056
case 5:
1057
if (isa != rv32) {
1077
- op = rv_op_c_addw;
1058
+ return &op_c_addw;
1059
}
1060
break;
1080
- case 6: op = rv_op_c_mul; break;
1061
+ case 6: return &op_c_mul;
1062
case 7:
1063
switch ((inst >> 2) & 0b111) {
1083
- case 0: op = rv_op_c_zext_b; break;
1084
- case 1: op = rv_op_c_sext_b; break;
1085
- case 2: op = rv_op_c_zext_h; break;
1086
- case 3: op = rv_op_c_sext_h; break;
1087
- case 4: op = rv_op_c_zext_w; break;
1088
- case 5: op = rv_op_c_not; break;
1064
+ case 0: return &op_c_zext_b;
1065
+ case 1: return &op_c_sext_b;
1066
+ case 2: return &op_c_zext_h;
1067
+ case 3: return &op_c_sext_h;
1068
+ case 4: return &op_c_zext_w;
1069
+ case 5: return &op_c_not;
1070
}
1071
break;
1072
}
1073
break;
1074
}
1075
break;
1095
- case 5: op = rv_op_c_j; break;
1096
- case 6: op = rv_op_c_beqz; break;
1097
- case 7: op = rv_op_c_bnez; break;
1076
+ case 5: return &op_c_j;
1077
+ case 6: return &op_c_beqz;
1078
+ case 7: return &op_c_bnez;
1079
}
1080
break;
1081
case 2:
1082
switch ((inst >> 13) & 0b111) {
1083
case 0:
1084
if (isa != rv32 || (inst & 0x1000) == 0) {
1104
- op = rv_op_c_slli; /* or unspecified HINT */
1085
+ return &op_c_slli; /* or unspecified HINT */
1086
}
1087
break;
1088
case 1:
1089
if (isa == rv128) {
1109
- op = rv_op_c_lqsp;
1110
- } else {
1111
- op = rv_op_c_fldsp;
1090
+ return &op_c_lqsp;
1091
}
1113
- break;
1114
- case 2: op = rv_op_c_lwsp; break;
1092
+ return &op_c_fldsp;
1093
+ case 2: return &op_c_lwsp;
1094
case 3:
1095
if (isa == rv32) {
1117
- op = rv_op_c_flwsp;
1118
- } else {
1119
- op = rv_op_c_ldsp;
1096
+ return &op_c_flwsp;
1097
}
1121
- break;
1098
+ return &op_c_ldsp;
1099
case 4:
1100
switch ((inst >> 12) & 0b1) {
1101
case 0:
1102
switch ((inst >> 2) & 0b11111) {
1126
- case 0: op = rv_op_c_jr; break;
1127
- default: op = rv_op_c_mv; break;
1103
+ case 0: return &op_c_jr;
1104
+ default: return &op_c_mv;
1105
}
1106
break;
1107
case 1:
1108
switch ((inst >> 2) & 0b11111) {
1109
case 0:
1110
switch ((inst >> 7) & 0b11111) {
1134
- case 0: op = rv_op_c_ebreak; break;
1135
- default: op = rv_op_c_jalr; break;
1111
+ case 0: return &op_c_ebreak;
1112
+ default: return &op_c_jalr;
1113
}
1114
break;
1138
- default: op = rv_op_c_add; break;
1115
+ default: return &op_c_add;
1116
}
1117
break;
1118
}
1119
break;
1120
case 5:
1121
if (isa == rv128) {
1145
- op = rv_op_c_sqsp;
1146
- } else {
1147
- op = rv_op_c_fsdsp;
1148
- if (dec->cfg && dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
1122
+ return &op_c_sqsp;
1123
+ }
1124
+ if (dec->cfg) {
1125
+ if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
1126
switch ((inst >> 8) & 0b01111) {
1127
case 8:
1128
if (((inst >> 4) & 0b01111) >= 4) {
1152
- op = rv_op_cm_push;
1129
+ return &op_cm_push;
1130
}
1131
break;
1132
case 10:
1133
if (((inst >> 4) & 0b01111) >= 4) {
1157
- op = rv_op_cm_pop;
1134
+ return &op_cm_pop;
1135
}
1136
break;
1137
case 12:
1138
if (((inst >> 4) & 0b01111) >= 4) {
1162
- op = rv_op_cm_popretz;
1139
+ return &op_cm_popretz;
1140
}
1141
break;
1142
case 14:
1143
if (((inst >> 4) & 0b01111) >= 4) {
1167
- op = rv_op_cm_popret;
1144
+ return &op_cm_popret;
1145
}
1146
break;
1147
}
1171
- } else {
1172
- switch ((inst >> 10) & 0b011) {
1173
- case 0:
1174
- if (dec->cfg && !dec->cfg->ext_zcmt) {
1175
- break;
1176
- }
1177
- if (((inst >> 2) & 0xFF) >= 32) {
1178
- op = rv_op_cm_jalt;
1179
- } else {
1180
- op = rv_op_cm_jt;
1181
- }
1148
+ }
1149
+ switch ((inst >> 10) & 0b011) {
1150
+ case 0:
1151
+ if (!dec->cfg->ext_zcmt) {
1152
break;
1183
- case 3:
1184
- if (dec->cfg && !dec->cfg->ext_zcmp) {
1185
- break;
1186
- }
1187
- switch ((inst >> 5) & 0b011) {
1188
- case 1: op = rv_op_cm_mvsa01; break;
1189
- case 3: op = rv_op_cm_mva01s; break;
1190
- }
1153
+ }
1154
+ if (((inst >> 2) & 0xFF) >= 32) {
1155
+ return &op_cm_jalt;
1156
+ }
1157
+ return &op_cm_jt;
1158
+ case 3:
1159
+ if (!dec->cfg->ext_zcmp) {
1160
break;
1161
}
1162
+ switch ((inst >> 5) & 0b011) {
1163
+ case 1: return &op_cm_mvsa01;
1164
+ case 3: return &op_cm_mva01s;
1165
+ }
1166
+ break;
1167
}
1168
}
1195
- break;
1196
- case 6: op = rv_op_c_swsp; break;
1169
+ return &op_c_fsdsp;
1170
+ case 6: return &op_c_swsp;
1171
case 7:
1172
if (isa == rv32) {
1199
- op = rv_op_c_fswsp;
1200
- } else {
1201
- op = rv_op_c_sdsp;
1173
+ return &op_c_fswsp;
1174
}
1203
- break;
1175
+ return &op_c_sdsp;
1176
}
1177
break;
1178
case 3:
1179
switch ((inst >> 2) & 0b11111) {
1180
case 0:
1181
switch ((inst >> 12) & 0b111) {
1210
- case 0: op = rv_op_lb; break;
1211
- case 1: op = rv_op_lh; break;
1212
- case 2: op = rv_op_lw; break;
1213
- case 3: op = rv_op_ld; break;
1214
- case 4: op = rv_op_lbu; break;
1215
- case 5: op = rv_op_lhu; break;
1216
- case 6: op = rv_op_lwu; break;
1217
- case 7: op = rv_op_ldu; break;
1182
+ case 0: return &op_lb;
1183
+ case 1: return &op_lh;
1184
+ case 2: return &op_lw;
1185
+ case 3: return &op_ld;
1186
+ case 4: return &op_lbu;
1187
+ case 5: return &op_lhu;
1188
+ case 6: return &op_lwu;
1189
+ case 7: return &op_ldu;
1190
}
1191
break;
1192
case 1:
1193
switch ((inst >> 12) & 0b111) {
1194
case 0:
1195
switch ((inst >> 20) & 0b111111111111) {
1224
- case 40: op = rv_op_vl1re8_v; break;
1225
- case 552: op = rv_op_vl2re8_v; break;
1226
- case 1576: op = rv_op_vl4re8_v; break;
1227
- case 3624: op = rv_op_vl8re8_v; break;
1196
+ case 40: return &op_vl1re8_v;
1197
+ case 552: return &op_vl2re8_v;
1198
+ case 1576: return &op_vl4re8_v;
1199
+ case 3624: return &op_vl8re8_v;
1200
}
1201
switch ((inst >> 26) & 0b111) {
1202
case 0:
1203
switch ((inst >> 20) & 0b11111) {
1232
- case 0: op = rv_op_vle8_v; break;
1233
- case 11: op = rv_op_vlm_v; break;
1234
- case 16: op = rv_op_vle8ff_v; break;
1204
+ case 0: return &op_vle8_v;
1205
+ case 11: return &op_vlm_v;
1206
+ case 16: return &op_vle8ff_v;
1207
}
1208
break;
1237
- case 1: op = rv_op_vluxei8_v; break;
1238
- case 2: op = rv_op_vlse8_v; break;
1239
- case 3: op = rv_op_vloxei8_v; break;
1209
+ case 1: return &op_vluxei8_v;
1210
+ case 2: return &op_vlse8_v;
1211
+ case 3: return &op_vloxei8_v;
1212
}
1213
break;
1242
- case 1: op = rv_op_flh; break;
1243
- case 2: op = rv_op_flw; break;
1244
- case 3: op = rv_op_fld; break;
1245
- case 4: op = rv_op_flq; break;
1214
+ case 1: return &op_flh;
1215
+ case 2: return &op_flw;
1216
+ case 3: return &op_fld;
1217
+ case 4: return &op_flq;
1218
case 5:
1219
switch ((inst >> 20) & 0b111111111111) {
1248
- case 40: op = rv_op_vl1re16_v; break;
1249
- case 552: op = rv_op_vl2re16_v; break;
1250
- case 1576: op = rv_op_vl4re16_v; break;
1251
- case 3624: op = rv_op_vl8re16_v; break;
1220
+ case 40: return &op_vl1re16_v;
1221
+ case 552: return &op_vl2re16_v;
1222
+ case 1576: return &op_vl4re16_v;
1223
+ case 3624: return &op_vl8re16_v;
1224
}
1225
switch ((inst >> 26) & 0b111) {
1226
case 0:
1227
switch ((inst >> 20) & 0b11111) {
1256
- case 0: op = rv_op_vle16_v; break;
1257
- case 16: op = rv_op_vle16ff_v; break;
1228
+ case 0: return &op_vle16_v;
1229
+ case 16: return &op_vle16ff_v;
1230
}
1231
break;
1260
- case 1: op = rv_op_vluxei16_v; break;
1261
- case 2: op = rv_op_vlse16_v; break;
1262
- case 3: op = rv_op_vloxei16_v; break;
1232
+ case 1: return &op_vluxei16_v;
1233
+ case 2: return &op_vlse16_v;
1234
+ case 3: return &op_vloxei16_v;
1235
}
1236
break;
1237
case 6:
1238
switch ((inst >> 20) & 0b111111111111) {
1267
- case 40: op = rv_op_vl1re32_v; break;
1268
- case 552: op = rv_op_vl2re32_v; break;
1269
- case 1576: op = rv_op_vl4re32_v; break;
1270
- case 3624: op = rv_op_vl8re32_v; break;
1239
+ case 40: return &op_vl1re32_v;
1240
+ case 552: return &op_vl2re32_v;
1241
+ case 1576: return &op_vl4re32_v;
1242
+ case 3624: return &op_vl8re32_v;
1243
}
1244
switch ((inst >> 26) & 0b111) {
1245
case 0:
1246
switch ((inst >> 20) & 0b11111) {
1275
- case 0: op = rv_op_vle32_v; break;
1276
- case 16: op = rv_op_vle32ff_v; break;
1247
+ case 0: return &op_vle32_v;
1248
+ case 16: return &op_vle32ff_v;
1249
}
1250
break;
1279
- case 1: op = rv_op_vluxei32_v; break;
1280
- case 2: op = rv_op_vlse32_v; break;
1281
- case 3: op = rv_op_vloxei32_v; break;
1251
+ case 1: return &op_vluxei32_v;
1252
+ case 2: return &op_vlse32_v;
1253
+ case 3: return &op_vloxei32_v;
1254
}
1255
break;
1256
case 7:
1257
switch ((inst >> 20) & 0b111111111111) {
1286
- case 40: op = rv_op_vl1re64_v; break;
1287
- case 552: op = rv_op_vl2re64_v; break;
1288
- case 1576: op = rv_op_vl4re64_v; break;
1289
- case 3624: op = rv_op_vl8re64_v; break;
1258
+ case 40: return &op_vl1re64_v;
1259
+ case 552: return &op_vl2re64_v;
1260
+ case 1576: return &op_vl4re64_v;
1261
+ case 3624: return &op_vl8re64_v;
1262
}
1263
switch ((inst >> 26) & 0b111) {
1264
case 0:
1265
switch ((inst >> 20) & 0b11111) {
1294
- case 0: op = rv_op_vle64_v; break;
1295
- case 16: op = rv_op_vle64ff_v; break;
1266
+ case 0: return &op_vle64_v;
1267
+ case 16: return &op_vle64ff_v;
1268
}
1269
break;
1298
- case 1: op = rv_op_vluxei64_v; break;
1299
- case 2: op = rv_op_vlse64_v; break;
1300
- case 3: op = rv_op_vloxei64_v; break;
1270
+ case 1: return &op_vluxei64_v;
1271
+ case 2: return &op_vlse64_v;
1272
+ case 3: return &op_vloxei64_v;
1273
}
1274
break;
1275
}
1276
break;
1277
case 3:
1278
switch ((inst >> 12) & 0b111) {
1307
- case 0: op = rv_op_fence; break;
1308
- case 1: op = rv_op_fence_i; break;
1279
+ case 0: return &op_fence;
1280
+ case 1: return &op_fence_i;
1281
case 2:
1282
/*
1283
* 'lq' shares the "(...) 010 ..... 0001111" opcode space
@@ -1320,204 +1292,203 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
1292
* Anything that doesn't match these will default to 'lq'.
1293
*/
1294
switch ((inst >> 17) & 0b11111) {
1323
- case 0: op = rv_op_cbo_inval; break;
1324
- case 1: op = rv_op_cbo_clean; break;
1325
- case 2: op = rv_op_cbo_flush; break;
1326
- case 4: op = rv_op_cbo_zero; break;
1327
- default: op = rv_op_lq; break;
1295
+ case 0: return &op_cbo_inval;
1296
+ case 1: return &op_cbo_clean;
1297
+ case 2: return &op_cbo_flush;
1298
+ case 4: return &op_cbo_zero;
1299
+ default: return &op_lq;
1300
}
1301
}
1302
break;
1303
case 4:
1304
switch ((inst >> 12) & 0b111) {
1333
- case 0: op = rv_op_addi; break;
1305
+ case 0: return &op_addi;
1306
case 1:
1307
switch ((inst >> 27) & 0b11111) {
1336
- case 0b00000: op = rv_op_slli; break;
1308
+ case 0b00000: return &op_slli;
1309
case 0b00001:
1310
switch ((inst >> 20) & 0b1111111) {
1339
- case 0b0001111: op = rv_op_zip; break;
1311
+ case 0b0001111: return &op_zip;
1312
}
1313
break;
1314
case 0b00010:
1315
switch ((inst >> 20) & 0b1111111) {
1344
- case 0b0000000: op = rv_op_sha256sum0; break;
1345
- case 0b0000001: op = rv_op_sha256sum1; break;
1346
- case 0b0000010: op = rv_op_sha256sig0; break;
1347
- case 0b0000011: op = rv_op_sha256sig1; break;
1348
- case 0b0000100: op = rv_op_sha512sum0; break;
1349
- case 0b0000101: op = rv_op_sha512sum1; break;
1350
- case 0b0000110: op = rv_op_sha512sig0; break;
1351
- case 0b0000111: op = rv_op_sha512sig1; break;
1352
- case 0b0001000: op = rv_op_sm3p0; break;
1353
- case 0b0001001: op = rv_op_sm3p1; break;
1316
+ case 0b0000000: return &op_sha256sum0;
1317
+ case 0b0000001: return &op_sha256sum1;
1318
+ case 0b0000010: return &op_sha256sig0;
1319
+ case 0b0000011: return &op_sha256sig1;
1320
+ case 0b0000100: return &op_sha512sum0;
1321
+ case 0b0000101: return &op_sha512sum1;
1322
+ case 0b0000110: return &op_sha512sig0;
1323
+ case 0b0000111: return &op_sha512sig1;
1324
+ case 0b0001000: return &op_sm3p0;
1325
+ case 0b0001001: return &op_sm3p1;
1326
}
1327
break;
1356
- case 0b00101: op = rv_op_bseti; break;
1328
+ case 0b00101: return &op_bseti;
1329
case 0b00110:
1330
switch ((inst >> 20) & 0b1111111) {
1359
- case 0b0000000: op = rv_op_aes64im; break;
1331
+ case 0b0000000: return &op_aes64im;
1332
default:
1333
if (((inst >> 24) & 0b0111) == 0b001) {
1362
- op = rv_op_aes64ks1i;
1334
+ return &op_aes64ks1i;
1335
}
1336
break;
1337
}
1338
break;
1367
- case 0b01001: op = rv_op_bclri; break;
1368
- case 0b01101: op = rv_op_binvi; break;
1339
+ case 0b01001: return &op_bclri;
1340
+ case 0b01101: return &op_binvi;
1341
case 0b01100:
1342
switch ((inst >> 20) & 0b1111111) {
1371
- case 0b0000000: op = rv_op_clz; break;
1372
- case 0b0000001: op = rv_op_ctz; break;
1373
- case 0b0000010: op = rv_op_cpop; break;
1343
+ case 0b0000000: return &op_clz;
1344
+ case 0b0000001: return &op_ctz;
1345
+ case 0b0000010: return &op_cpop;
1346
/* 0b0000011 */
1375
- case 0b0000100: op = rv_op_sext_b; break;
1376
- case 0b0000101: op = rv_op_sext_h; break;
1347
+ case 0b0000100: return &op_sext_b;
1348
+ case 0b0000101: return &op_sext_h;
1349
}
1350
break;
1351
}
1352
break;
1381
- case 2: op = rv_op_slti; break;
1382
- case 3: op = rv_op_sltiu; break;
1383
- case 4: op = rv_op_xori; break;
1353
+ case 2: return &op_slti;
1354
+ case 3: return &op_sltiu;
1355
+ case 4: return &op_xori;
1356
case 5:
1357
switch ((inst >> 27) & 0b11111) {
1386
- case 0b00000: op = rv_op_srli; break;
1358
+ case 0b00000: return &op_srli;
1359
case 0b00001:
1360
switch ((inst >> 20) & 0b1111111) {
1389
- case 0b0001111: op = rv_op_unzip; break;
1361
+ case 0b0001111: return &op_unzip;
1362
}
1363
break;
1392
- case 0b00101: op = rv_op_orc_b; break;
1393
- case 0b01000: op = rv_op_srai; break;
1394
- case 0b01001: op = rv_op_bexti; break;
1395
- case 0b01100: op = rv_op_rori; break;
1364
+ case 0b00101: return &op_orc_b;
1365
+ case 0b01000: return &op_srai;
1366
+ case 0b01001: return &op_bexti;
1367
+ case 0b01100: return &op_rori;
1368
case 0b01101:
1369
switch ((inst >> 20) & 0b1111111) {
1370
case 0b0011000:
1371
if (isa == rv32) {
1400
- op = rv_op_rev8;
1372
+ return &op_rev8;
1373
}
1374
break;
1375
case 0b0111000:
1376
if (isa == rv64) {
1405
- op = rv_op_rev8;
1377
+ return &op_rev8;
1378
}
1379
break;
1408
- case 0b0000111: op = rv_op_brev8; break;
1380
+ case 0b0000111: return &op_brev8;
1381
}
1382
break;
1383
}
1384
break;
1413
- case 6: op = rv_op_ori; break;
1414
- case 7: op = rv_op_andi; break;
1385
+ case 6: return &op_ori;
1386
+ case 7: return &op_andi;
1387
}
1388
break;
1389
case 5:
1418
- op = rv_op_auipc;
1390
if (dec->cfg && dec->cfg->ext_zicfilp &&
1391
(((inst >> 7) & 0b11111) == 0b00000)) {
1421
- op = rv_op_lpad;
1392
+ return &op_lpad;
1393
}
1423
- break;
1394
+ return &op_auipc;
1395
case 6:
1396
/* OP-IMM-32 */
1397
if (isa == rv32) {
1398
break;
1399
}
1400
switch ((inst >> 12) & 0b111) {
1430
- case 0: op = rv_op_addiw; break;
1401
+ case 0: return &op_addiw;
1402
case 1:
1403
switch ((inst >> 26) & 0b111111) {
1433
- case 0: op = rv_op_slliw; break;
1434
- case 2: op = rv_op_slli_uw; break;
1404
+ case 0: return &op_slliw;
1405
+ case 2: return &op_slli_uw;
1406
case 24:
1407
switch ((inst >> 20) & 0b11111) {
1437
- case 0b00000: op = rv_op_clzw; break;
1438
- case 0b00001: op = rv_op_ctzw; break;
1439
- case 0b00010: op = rv_op_cpopw; break;
1408
+ case 0b00000: return &op_clzw;
1409
+ case 0b00001: return &op_ctzw;
1410
+ case 0b00010: return &op_cpopw;
1411
}
1412
break;
1413
}
1414
break;
1415
case 5:
1416
switch ((inst >> 25) & 0b1111111) {
1446
- case 0: op = rv_op_srliw; break;
1447
- case 32: op = rv_op_sraiw; break;
1448
- case 48: op = rv_op_roriw; break;
1417
+ case 0: return &op_srliw;
1418
+ case 32: return &op_sraiw;
1419
+ case 48: return &op_roriw;
1420
}
1421
break;
1422
}
1423
break;
1424
case 8:
1425
switch ((inst >> 12) & 0b111) {
1455
- case 0: op = rv_op_sb; break;
1456
- case 1: op = rv_op_sh; break;
1457
- case 2: op = rv_op_sw; break;
1458
- case 3: op = rv_op_sd; break;
1459
- case 4: op = rv_op_sq; break;
1426
+ case 0: return &op_sb;
1427
+ case 1: return &op_sh;
1428
+ case 2: return &op_sw;
1429
+ case 3: return &op_sd;
1430
+ case 4: return &op_sq;
1431
}
1432
break;
1433
case 9:
1434
switch ((inst >> 12) & 0b111) {
1435
case 0:
1436
switch ((inst >> 20) & 0b111111111111) {
1466
- case 40: op = rv_op_vs1r_v; break;
1467
- case 552: op = rv_op_vs2r_v; break;
1468
- case 1576: op = rv_op_vs4r_v; break;
1469
- case 3624: op = rv_op_vs8r_v; break;
1437
+ case 40: return &op_vs1r_v;
1438
+ case 552: return &op_vs2r_v;
1439
+ case 1576: return &op_vs4r_v;
1440
+ case 3624: return &op_vs8r_v;
1441
}
1442
switch ((inst >> 26) & 0b111) {
1443
case 0:
1444
switch ((inst >> 20) & 0b11111) {
1474
- case 0: op = rv_op_vse8_v; break;
1475
- case 11: op = rv_op_vsm_v; break;
1445
+ case 0: return &op_vse8_v;
1446
+ case 11: return &op_vsm_v;
1447
}
1448
break;
1478
- case 1: op = rv_op_vsuxei8_v; break;
1479
- case 2: op = rv_op_vsse8_v; break;
1480
- case 3: op = rv_op_vsoxei8_v; break;
1449
+ case 1: return &op_vsuxei8_v;
1450
+ case 2: return &op_vsse8_v;
1451
+ case 3: return &op_vsoxei8_v;
1452
}
1453
break;
1483
- case 1: op = rv_op_fsh; break;
1484
- case 2: op = rv_op_fsw; break;
1485
- case 3: op = rv_op_fsd; break;
1486
- case 4: op = rv_op_fsq; break;
1454
+ case 1: return &op_fsh;
1455
+ case 2: return &op_fsw;
1456
+ case 3: return &op_fsd;
1457
+ case 4: return &op_fsq;
1458
case 5:
1459
switch ((inst >> 26) & 0b111) {
1460
case 0:
1461
switch ((inst >> 20) & 0b11111) {
1491
- case 0: op = rv_op_vse16_v; break;
1462
+ case 0: return &op_vse16_v;
1463
}
1464
break;
1494
- case 1: op = rv_op_vsuxei16_v; break;
1495
- case 2: op = rv_op_vsse16_v; break;
1496
- case 3: op = rv_op_vsoxei16_v; break;
1465
+ case 1: return &op_vsuxei16_v;
1466
+ case 2: return &op_vsse16_v;
1467
+ case 3: return &op_vsoxei16_v;
1468
}
1469
break;
1470
case 6:
1471
switch ((inst >> 26) & 0b111) {
1472
case 0:
1473
switch ((inst >> 20) & 0b11111) {
1503
- case 0: op = rv_op_vse32_v; break;
1474
+ case 0: return &op_vse32_v;
1475
}
1476
break;
1506
- case 1: op = rv_op_vsuxei32_v; break;
1507
- case 2: op = rv_op_vsse32_v; break;
1508
- case 3: op = rv_op_vsoxei32_v; break;
1477
+ case 1: return &op_vsuxei32_v;
1478
+ case 2: return &op_vsse32_v;
1479
+ case 3: return &op_vsoxei32_v;
1480
}
1481
break;
1482
case 7:
1483
switch ((inst >> 26) & 0b111) {
1484
case 0:
1485
switch ((inst >> 20) & 0b11111) {
1515
- case 0: op = rv_op_vse64_v; break;
1486
+ case 0: return &op_vse64_v;
1487
}
1488
break;
1518
- case 1: op = rv_op_vsuxei64_v; break;
1519
- case 2: op = rv_op_vsse64_v; break;
1520
- case 3: op = rv_op_vsoxei64_v; break;
1489
+ case 1: return &op_vsuxei64_v;
1490
+ case 2: return &op_vsse64_v;
1491
+ case 3: return &op_vsoxei64_v;
1492
}
1493
break;
1494
}
@@ -1525,153 +1496,150 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
1496
case 11:
1497
switch (((inst >> 24) & 0b11111000) |
1498
((inst >> 12) & 0b00000111)) {
1528
- case 0: op = rv_op_amoadd_b; break;
1529
- case 1: op = rv_op_amoadd_h; break;
1530
- case 2: op = rv_op_amoadd_w; break;
1531
- case 3: op = rv_op_amoadd_d; break;
1532
- case 4: op = rv_op_amoadd_q; break;
1533
- case 8: op = rv_op_amoswap_b; break;
1534
- case 9: op = rv_op_amoswap_h; break;
1535
- case 10: op = rv_op_amoswap_w; break;
1536
- case 11: op = rv_op_amoswap_d; break;
1537
- case 12: op = rv_op_amoswap_q; break;
1499
+ case 0: return &op_amoadd_b;
1500
+ case 1: return &op_amoadd_h;
1501
+ case 2: return &op_amoadd_w;
1502
+ case 3: return &op_amoadd_d;
1503
+ case 4: return &op_amoadd_q;
1504
+ case 8: return &op_amoswap_b;
1505
+ case 9: return &op_amoswap_h;
1506
+ case 10: return &op_amoswap_w;
1507
+ case 11: return &op_amoswap_d;
1508
+ case 12: return &op_amoswap_q;
1509
case 18:
1510
switch ((inst >> 20) & 0b11111) {
1540
- case 0: op = rv_op_lr_w; break;
1511
+ case 0: return &op_lr_w;
1512
}
1513
break;
1514
case 19:
1515
switch ((inst >> 20) & 0b11111) {
1545
- case 0: op = rv_op_lr_d; break;
1516
+ case 0: return &op_lr_d;
1517
}
1518
break;
1519
case 20:
1520
switch ((inst >> 20) & 0b11111) {
1550
- case 0: op = rv_op_lr_q; break;
1551
- }
1552
- break;
1553
- case 26: op = rv_op_sc_w; break;
1554
- case 27: op = rv_op_sc_d; break;
1555
- case 28: op = rv_op_sc_q; break;
1556
- case 32: op = rv_op_amoxor_b; break;
1557
- case 33: op = rv_op_amoxor_h; break;
1558
- case 34: op = rv_op_amoxor_w; break;
1559
- case 35: op = rv_op_amoxor_d; break;
1560
- case 36: op = rv_op_amoxor_q; break;
1561
- case 40: op = rv_op_amocas_b; break;
1562
- case 41: op = rv_op_amocas_h; break;
1563
- case 42: op = rv_op_amocas_w; break;
1564
- case 43: op = rv_op_amocas_d; break;
1565
- case 44: op = rv_op_amocas_q; break;
1566
- case 64: op = rv_op_amoor_b; break;
1567
- case 65: op = rv_op_amoor_h; break;
1568
- case 66: op = rv_op_amoor_w; break;
1569
- case 67: op = rv_op_amoor_d; break;
1570
- case 68: op = rv_op_amoor_q; break;
1571
- case 74: op = rv_op_ssamoswap_w; break;
1572
- case 75: op = rv_op_ssamoswap_d; break;
1573
- case 96: op = rv_op_amoand_b; break;
1574
- case 97: op = rv_op_amoand_h; break;
1575
- case 98: op = rv_op_amoand_w; break;
1576
- case 99: op = rv_op_amoand_d; break;
1577
- case 100: op = rv_op_amoand_q; break;
1578
- case 128: op = rv_op_amomin_b; break;
1579
- case 129: op = rv_op_amomin_h; break;
1580
- case 130: op = rv_op_amomin_w; break;
1581
- case 131: op = rv_op_amomin_d; break;
1582
- case 132: op = rv_op_amomin_q; break;
1583
- case 160: op = rv_op_amomax_b; break;
1584
- case 161: op = rv_op_amomax_h; break;
1585
- case 162: op = rv_op_amomax_w; break;
1586
- case 163: op = rv_op_amomax_d; break;
1587
- case 164: op = rv_op_amomax_q; break;
1588
- case 192: op = rv_op_amominu_b; break;
1589
- case 193: op = rv_op_amominu_h; break;
1590
- case 194: op = rv_op_amominu_w; break;
1591
- case 195: op = rv_op_amominu_d; break;
1592
- case 196: op = rv_op_amominu_q; break;
1593
- case 224: op = rv_op_amomaxu_b; break;
1594
- case 225: op = rv_op_amomaxu_h; break;
1595
- case 226: op = rv_op_amomaxu_w; break;
1596
- case 227: op = rv_op_amomaxu_d; break;
1597
- case 228: op = rv_op_amomaxu_q; break;
1521
+ case 0: return &op_lr_q;
1522
+ }
1523
+ break;
1524
+ case 26: return &op_sc_w;
1525
+ case 27: return &op_sc_d;
1526
+ case 28: return &op_sc_q;
1527
+ case 32: return &op_amoxor_b;
1528
+ case 33: return &op_amoxor_h;
1529
+ case 34: return &op_amoxor_w;
1530
+ case 35: return &op_amoxor_d;
1531
+ case 36: return &op_amoxor_q;
1532
+ case 40: return &op_amocas_b;
1533
+ case 41: return &op_amocas_h;
1534
+ case 42: return &op_amocas_w;
1535
+ case 43: return &op_amocas_d;
1536
+ case 44: return &op_amocas_q;
1537
+ case 64: return &op_amoor_b;
1538
+ case 65: return &op_amoor_h;
1539
+ case 66: return &op_amoor_w;
1540
+ case 67: return &op_amoor_d;
1541
+ case 68: return &op_amoor_q;
1542
+ case 74: return &op_ssamoswap_w;
1543
+ case 75: return &op_ssamoswap_d;
1544
+ case 96: return &op_amoand_b;
1545
+ case 97: return &op_amoand_h;
1546
+ case 98: return &op_amoand_w;
1547
+ case 99: return &op_amoand_d;
1548
+ case 100: return &op_amoand_q;
1549
+ case 128: return &op_amomin_b;
1550
+ case 129: return &op_amomin_h;
1551
+ case 130: return &op_amomin_w;
1552
+ case 131: return &op_amomin_d;
1553
+ case 132: return &op_amomin_q;
1554
+ case 160: return &op_amomax_b;
1555
+ case 161: return &op_amomax_h;
1556
+ case 162: return &op_amomax_w;
1557
+ case 163: return &op_amomax_d;
1558
+ case 164: return &op_amomax_q;
1559
+ case 192: return &op_amominu_b;
1560
+ case 193: return &op_amominu_h;
1561
+ case 194: return &op_amominu_w;
1562
+ case 195: return &op_amominu_d;
1563
+ case 196: return &op_amominu_q;
1564
+ case 224: return &op_amomaxu_b;
1565
+ case 225: return &op_amomaxu_h;
1566
+ case 226: return &op_amomaxu_w;
1567
+ case 227: return &op_amomaxu_d;
1568
+ case 228: return &op_amomaxu_q;
1569
}
1570
break;
1571
case 12:
1572
switch (((inst >> 22) & 0b1111111000) |
1573
((inst >> 12) & 0b0000000111)) {
1603
- case 0: op = rv_op_add; break;
1604
- case 1: op = rv_op_sll; break;
1605
- case 2: op = rv_op_slt; break;
1606
- case 3: op = rv_op_sltu; break;
1607
- case 4: op = rv_op_xor; break;
1608
- case 5: op = rv_op_srl; break;
1609
- case 6: op = rv_op_or; break;
1610
- case 7: op = rv_op_and; break;
1611
- case 8: op = rv_op_mul; break;
1612
- case 9: op = rv_op_mulh; break;
1613
- case 10: op = rv_op_mulhsu; break;
1614
- case 11: op = rv_op_mulhu; break;
1615
- case 12: op = rv_op_div; break;
1616
- case 13: op = rv_op_divu; break;
1617
- case 14: op = rv_op_rem; break;
1618
- case 15: op = rv_op_remu; break;
1574
+ case 0: return &op_add;
1575
+ case 1: return &op_sll;
1576
+ case 2: return &op_slt;
1577
+ case 3: return &op_sltu;
1578
+ case 4: return &op_xor;
1579
+ case 5: return &op_srl;
1580
+ case 6: return &op_or;
1581
+ case 7: return &op_and;
1582
+ case 8: return &op_mul;
1583
+ case 9: return &op_mulh;
1584
+ case 10: return &op_mulhsu;
1585
+ case 11: return &op_mulhu;
1586
+ case 12: return &op_div;
1587
+ case 13: return &op_divu;
1588
+ case 14: return &op_rem;
1589
+ case 15: return &op_remu;
1590
case 36:
1591
if (isa == rv32 && !((inst >> 20) & 0b11111)) {
1621
- op = rv_op_zext_h;
1622
- } else {
1623
- op = rv_op_pack;
1624
- }
1625
- break;
1626
- case 39: op = rv_op_packh; break;
1627
-
1628
- case 41: op = rv_op_clmul; break;
1629
- case 42: op = rv_op_clmulr; break;
1630
- case 43: op = rv_op_clmulh; break;
1631
- case 44: op = rv_op_min; break;
1632
- case 45: op = rv_op_minu; break;
1633
- case 46: op = rv_op_max; break;
1634
- case 47: op = rv_op_maxu; break;
1635
- case 075: op = rv_op_czero_eqz; break;
1636
- case 077: op = rv_op_czero_nez; break;
1637
- case 130: op = rv_op_sh1add; break;
1638
- case 132: op = rv_op_sh2add; break;
1639
- case 134: op = rv_op_sh3add; break;
1640
- case 161: op = rv_op_bset; break;
1641
- case 162: op = rv_op_xperm4; break;
1642
- case 164: op = rv_op_xperm8; break;
1643
- case 200: op = rv_op_aes64es; break;
1644
- case 216: op = rv_op_aes64esm; break;
1645
- case 232: op = rv_op_aes64ds; break;
1646
- case 248: op = rv_op_aes64dsm; break;
1647
- case 256: op = rv_op_sub; break;
1648
- case 260: op = rv_op_xnor; break;
1649
- case 261: op = rv_op_sra; break;
1650
- case 262: op = rv_op_orn; break;
1651
- case 263: op = rv_op_andn; break;
1652
- case 289: op = rv_op_bclr; break;
1653
- case 293: op = rv_op_bext; break;
1654
- case 320: op = rv_op_sha512sum0r; break;
1655
- case 328: op = rv_op_sha512sum1r; break;
1656
- case 336: op = rv_op_sha512sig0l; break;
1657
- case 344: op = rv_op_sha512sig1l; break;
1658
- case 368: op = rv_op_sha512sig0h; break;
1659
- case 376: op = rv_op_sha512sig1h; break;
1660
- case 385: op = rv_op_rol; break;
1661
- case 389: op = rv_op_ror; break;
1662
- case 417: op = rv_op_binv; break;
1663
- case 504: op = rv_op_aes64ks2; break;
1592
+ return &op_zext_h;
1593
+ }
1594
+ return &op_pack;
1595
+ case 39: return &op_packh;
1596
+ case 41: return &op_clmul;
1597
+ case 42: return &op_clmulr;
1598
+ case 43: return &op_clmulh;
1599
+ case 44: return &op_min;
1600
+ case 45: return &op_minu;
1601
+ case 46: return &op_max;
1602
+ case 47: return &op_maxu;
1603
+ case 075: return &op_czero_eqz;
1604
+ case 077: return &op_czero_nez;
1605
+ case 130: return &op_sh1add;
1606
+ case 132: return &op_sh2add;
1607
+ case 134: return &op_sh3add;
1608
+ case 161: return &op_bset;
1609
+ case 162: return &op_xperm4;
1610
+ case 164: return &op_xperm8;
1611
+ case 200: return &op_aes64es;
1612
+ case 216: return &op_aes64esm;
1613
+ case 232: return &op_aes64ds;
1614
+ case 248: return &op_aes64dsm;
1615
+ case 256: return &op_sub;
1616
+ case 260: return &op_xnor;
1617
+ case 261: return &op_sra;
1618
+ case 262: return &op_orn;
1619
+ case 263: return &op_andn;
1620
+ case 289: return &op_bclr;
1621
+ case 293: return &op_bext;
1622
+ case 320: return &op_sha512sum0r;
1623
+ case 328: return &op_sha512sum1r;
1624
+ case 336: return &op_sha512sig0l;
1625
+ case 344: return &op_sha512sig1l;
1626
+ case 368: return &op_sha512sig0h;
1627
+ case 376: return &op_sha512sig1h;
1628
+ case 385: return &op_rol;
1629
+ case 389: return &op_ror;
1630
+ case 417: return &op_binv;
1631
+ case 504: return &op_aes64ks2;
1632
}
1633
switch ((inst >> 25) & 0b0011111) {
1666
- case 17: op = rv_op_aes32esi; break;
1667
- case 19: op = rv_op_aes32esmi; break;
1668
- case 21: op = rv_op_aes32dsi; break;
1669
- case 23: op = rv_op_aes32dsmi; break;
1670
- case 24: op = rv_op_sm4ed; break;
1671
- case 26: op = rv_op_sm4ks; break;
1634
+ case 17: return &op_aes32esi;
1635
+ case 19: return &op_aes32esmi;
1636
+ case 21: return &op_aes32dsi;
1637
+ case 23: return &op_aes32dsmi;
1638
+ case 24: return &op_sm4ed;
1639
+ case 26: return &op_sm4ks;
1640
}
1641
break;
1674
- case 13: op = rv_op_lui; break;
1642
+ case 13: return &op_lui;
1643
case 14:
1644
/* OP-32 */
1645
if (isa == rv32) {
@@ -1679,317 +1647,317 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
1647
}
1648
switch (((inst >> 22) & 0b1111111000) |
1649
((inst >> 12) & 0b0000000111)) {
1682
- case 0: op = rv_op_addw; break;
1683
- case 1: op = rv_op_sllw; break;
1684
- case 5: op = rv_op_srlw; break;
1685
- case 8: op = rv_op_mulw; break;
1686
- case 12: op = rv_op_divw; break;
1687
- case 13: op = rv_op_divuw; break;
1688
- case 14: op = rv_op_remw; break;
1689
- case 15: op = rv_op_remuw; break;
1690
- case 32: op = rv_op_add_uw; break;
1650
+ case 0: return &op_addw;
1651
+ case 1: return &op_sllw;
1652
+ case 5: return &op_srlw;
1653
+ case 8: return &op_mulw;
1654
+ case 12: return &op_divw;
1655
+ case 13: return &op_divuw;
1656
+ case 14: return &op_remw;
1657
+ case 15: return &op_remuw;
1658
+ case 32: return &op_add_uw;
1659
case 36:
1660
switch ((inst >> 20) & 0b11111) {
1693
- case 0: op = rv_op_zext_h; break;
1694
- default: op = rv_op_packw; break;
1661
+ case 0: return &op_zext_h;
1662
+ default: return &op_packw;
1663
}
1664
break;
1697
- case 130: op = rv_op_sh1add_uw; break;
1698
- case 132: op = rv_op_sh2add_uw; break;
1699
- case 134: op = rv_op_sh3add_uw; break;
1700
- case 256: op = rv_op_subw; break;
1701
- case 261: op = rv_op_sraw; break;
1702
- case 385: op = rv_op_rolw; break;
1703
- case 389: op = rv_op_rorw; break;
1665
+ case 130: return &op_sh1add_uw;
1666
+ case 132: return &op_sh2add_uw;
1667
+ case 134: return &op_sh3add_uw;
1668
+ case 256: return &op_subw;
1669
+ case 261: return &op_sraw;
1670
+ case 385: return &op_rolw;
1671
+ case 389: return &op_rorw;
1672
}
1673
break;
1674
case 16:
1675
switch ((inst >> 25) & 0b11) {
1708
- case 0: op = rv_op_fmadd_s; break;
1709
- case 1: op = rv_op_fmadd_d; break;
1710
- case 3: op = rv_op_fmadd_q; break;
1676
+ case 0: return &op_fmadd_s;
1677
+ case 1: return &op_fmadd_d;
1678
+ case 3: return &op_fmadd_q;
1679
}
1680
break;
1681
case 17:
1682
switch ((inst >> 25) & 0b11) {
1715
- case 0: op = rv_op_fmsub_s; break;
1716
- case 1: op = rv_op_fmsub_d; break;
1717
- case 3: op = rv_op_fmsub_q; break;
1683
+ case 0: return &op_fmsub_s;
1684
+ case 1: return &op_fmsub_d;
1685
+ case 3: return &op_fmsub_q;
1686
}
1687
break;
1688
case 18:
1689
switch ((inst >> 25) & 0b11) {
1722
- case 0: op = rv_op_fnmsub_s; break;
1723
- case 1: op = rv_op_fnmsub_d; break;
1724
- case 3: op = rv_op_fnmsub_q; break;
1690
+ case 0: return &op_fnmsub_s;
1691
+ case 1: return &op_fnmsub_d;
1692
+ case 3: return &op_fnmsub_q;
1693
}
1694
break;
1695
case 19:
1696
switch ((inst >> 25) & 0b11) {
1729
- case 0: op = rv_op_fnmadd_s; break;
1730
- case 1: op = rv_op_fnmadd_d; break;
1731
- case 3: op = rv_op_fnmadd_q; break;
1697
+ case 0: return &op_fnmadd_s;
1698
+ case 1: return &op_fnmadd_d;
1699
+ case 3: return &op_fnmadd_q;
1700
}
1701
break;
1702
case 20:
1703
switch ((inst >> 25) & 0b1111111) {
1736
- case 0: op = rv_op_fadd_s; break;
1737
- case 1: op = rv_op_fadd_d; break;
1738
- case 3: op = rv_op_fadd_q; break;
1739
- case 4: op = rv_op_fsub_s; break;
1740
- case 5: op = rv_op_fsub_d; break;
1741
- case 7: op = rv_op_fsub_q; break;
1742
- case 8: op = rv_op_fmul_s; break;
1743
- case 9: op = rv_op_fmul_d; break;
1744
- case 11: op = rv_op_fmul_q; break;
1745
- case 12: op = rv_op_fdiv_s; break;
1746
- case 13: op = rv_op_fdiv_d; break;
1747
- case 15: op = rv_op_fdiv_q; break;
1704
+ case 0: return &op_fadd_s;
1705
+ case 1: return &op_fadd_d;
1706
+ case 3: return &op_fadd_q;
1707
+ case 4: return &op_fsub_s;
1708
+ case 5: return &op_fsub_d;
1709
+ case 7: return &op_fsub_q;
1710
+ case 8: return &op_fmul_s;
1711
+ case 9: return &op_fmul_d;
1712
+ case 11: return &op_fmul_q;
1713
+ case 12: return &op_fdiv_s;
1714
+ case 13: return &op_fdiv_d;
1715
+ case 15: return &op_fdiv_q;
1716
case 16:
1717
switch ((inst >> 12) & 0b111) {
1750
- case 0: op = rv_op_fsgnj_s; break;
1751
- case 1: op = rv_op_fsgnjn_s; break;
1752
- case 2: op = rv_op_fsgnjx_s; break;
1718
+ case 0: return &op_fsgnj_s;
1719
+ case 1: return &op_fsgnjn_s;
1720
+ case 2: return &op_fsgnjx_s;
1721
}
1722
break;
1723
case 17:
1724
switch ((inst >> 12) & 0b111) {
1757
- case 0: op = rv_op_fsgnj_d; break;
1758
- case 1: op = rv_op_fsgnjn_d; break;
1759
- case 2: op = rv_op_fsgnjx_d; break;
1725
+ case 0: return &op_fsgnj_d;
1726
+ case 1: return &op_fsgnjn_d;
1727
+ case 2: return &op_fsgnjx_d;
1728
}
1729
break;
1730
case 19:
1731
switch ((inst >> 12) & 0b111) {
1764
- case 0: op = rv_op_fsgnj_q; break;
1765
- case 1: op = rv_op_fsgnjn_q; break;
1766
- case 2: op = rv_op_fsgnjx_q; break;
1732
+ case 0: return &op_fsgnj_q;
1733
+ case 1: return &op_fsgnjn_q;
1734
+ case 2: return &op_fsgnjx_q;
1735
}
1736
break;
1737
case 20:
1738
switch ((inst >> 12) & 0b111) {
1771
- case 0: op = rv_op_fmin_s; break;
1772
- case 1: op = rv_op_fmax_s; break;
1773
- case 2: op = rv_op_fminm_s; break;
1774
- case 3: op = rv_op_fmaxm_s; break;
1739
+ case 0: return &op_fmin_s;
1740
+ case 1: return &op_fmax_s;
1741
+ case 2: return &op_fminm_s;
1742
+ case 3: return &op_fmaxm_s;
1743
}
1744
break;
1745
case 21:
1746
switch ((inst >> 12) & 0b111) {
1779
- case 0: op = rv_op_fmin_d; break;
1780
- case 1: op = rv_op_fmax_d; break;
1781
- case 2: op = rv_op_fminm_d; break;
1782
- case 3: op = rv_op_fmaxm_d; break;
1747
+ case 0: return &op_fmin_d;
1748
+ case 1: return &op_fmax_d;
1749
+ case 2: return &op_fminm_d;
1750
+ case 3: return &op_fmaxm_d;
1751
}
1752
break;
1753
case 22:
1754
switch (((inst >> 12) & 0b111)) {
1787
- case 2: op = rv_op_fminm_h; break;
1788
- case 3: op = rv_op_fmaxm_h; break;
1755
+ case 2: return &op_fminm_h;
1756
+ case 3: return &op_fmaxm_h;
1757
}
1758
break;
1759
case 23:
1760
switch ((inst >> 12) & 0b111) {
1793
- case 0: op = rv_op_fmin_q; break;
1794
- case 1: op = rv_op_fmax_q; break;
1795
- case 2: op = rv_op_fminm_q; break;
1796
- case 3: op = rv_op_fmaxm_q; break;
1761
+ case 0: return &op_fmin_q;
1762
+ case 1: return &op_fmax_q;
1763
+ case 2: return &op_fminm_q;
1764
+ case 3: return &op_fmaxm_q;
1765
}
1766
break;
1767
case 32:
1768
switch ((inst >> 20) & 0b11111) {
1801
- case 1: op = rv_op_fcvt_s_d; break;
1802
- case 3: op = rv_op_fcvt_s_q; break;
1803
- case 4: op = rv_op_fround_s; break;
1804
- case 5: op = rv_op_froundnx_s; break;
1805
- case 6: op = rv_op_fcvt_s_bf16; break;
1769
+ case 1: return &op_fcvt_s_d;
1770
+ case 3: return &op_fcvt_s_q;
1771
+ case 4: return &op_fround_s;
1772
+ case 5: return &op_froundnx_s;
1773
+ case 6: return &op_fcvt_s_bf16;
1774
}
1775
break;
1776
case 33:
1777
switch ((inst >> 20) & 0b11111) {
1810
- case 0: op = rv_op_fcvt_d_s; break;
1811
- case 3: op = rv_op_fcvt_d_q; break;
1812
- case 4: op = rv_op_fround_d; break;
1813
- case 5: op = rv_op_froundnx_d; break;
1778
+ case 0: return &op_fcvt_d_s;
1779
+ case 3: return &op_fcvt_d_q;
1780
+ case 4: return &op_fround_d;
1781
+ case 5: return &op_froundnx_d;
1782
}
1783
break;
1784
case 34:
1785
switch (((inst >> 20) & 0b11111)) {
1818
- case 4: op = rv_op_fround_h; break;
1819
- case 5: op = rv_op_froundnx_h; break;
1820
- case 8: op = rv_op_fcvt_bf16_s; break;
1786
+ case 4: return &op_fround_h;
1787
+ case 5: return &op_froundnx_h;
1788
+ case 8: return &op_fcvt_bf16_s;
1789
}
1790
break;
1791
case 35:
1792
switch ((inst >> 20) & 0b11111) {
1825
- case 0: op = rv_op_fcvt_q_s; break;
1826
- case 1: op = rv_op_fcvt_q_d; break;
1827
- case 4: op = rv_op_fround_q; break;
1828
- case 5: op = rv_op_froundnx_q; break;
1793
+ case 0: return &op_fcvt_q_s;
1794
+ case 1: return &op_fcvt_q_d;
1795
+ case 4: return &op_fround_q;
1796
+ case 5: return &op_froundnx_q;
1797
}
1798
break;
1799
case 44:
1800
switch ((inst >> 20) & 0b11111) {
1833
- case 0: op = rv_op_fsqrt_s; break;
1801
+ case 0: return &op_fsqrt_s;
1802
}
1803
break;
1804
case 45:
1805
switch ((inst >> 20) & 0b11111) {
1838
- case 0: op = rv_op_fsqrt_d; break;
1806
+ case 0: return &op_fsqrt_d;
1807
}
1808
break;
1809
case 47:
1810
switch ((inst >> 20) & 0b11111) {
1843
- case 0: op = rv_op_fsqrt_q; break;
1811
+ case 0: return &op_fsqrt_q;
1812
}
1813
break;
1814
case 80:
1815
switch ((inst >> 12) & 0b111) {
1848
- case 0: op = rv_op_fle_s; break;
1849
- case 1: op = rv_op_flt_s; break;
1850
- case 2: op = rv_op_feq_s; break;
1851
- case 4: op = rv_op_fleq_s; break;
1852
- case 5: op = rv_op_fltq_s; break;
1816
+ case 0: return &op_fle_s;
1817
+ case 1: return &op_flt_s;
1818
+ case 2: return &op_feq_s;
1819
+ case 4: return &op_fleq_s;
1820
+ case 5: return &op_fltq_s;
1821
}
1822
break;
1823
case 81:
1824
switch ((inst >> 12) & 0b111) {
1857
- case 0: op = rv_op_fle_d; break;
1858
- case 1: op = rv_op_flt_d; break;
1859
- case 2: op = rv_op_feq_d; break;
1860
- case 4: op = rv_op_fleq_d; break;
1861
- case 5: op = rv_op_fltq_d; break;
1825
+ case 0: return &op_fle_d;
1826
+ case 1: return &op_flt_d;
1827
+ case 2: return &op_feq_d;
1828
+ case 4: return &op_fleq_d;
1829
+ case 5: return &op_fltq_d;
1830
}
1831
break;
1832
case 82:
1833
switch (((inst >> 12) & 0b111)) {
1866
- case 4: op = rv_op_fleq_h; break;
1867
- case 5: op = rv_op_fltq_h; break;
1834
+ case 4: return &op_fleq_h;
1835
+ case 5: return &op_fltq_h;
1836
}
1837
break;
1838
case 83:
1839
switch ((inst >> 12) & 0b111) {
1872
- case 0: op = rv_op_fle_q; break;
1873
- case 1: op = rv_op_flt_q; break;
1874
- case 2: op = rv_op_feq_q; break;
1875
- case 4: op = rv_op_fleq_q; break;
1876
- case 5: op = rv_op_fltq_q; break;
1840
+ case 0: return &op_fle_q;
1841
+ case 1: return &op_flt_q;
1842
+ case 2: return &op_feq_q;
1843
+ case 4: return &op_fleq_q;
1844
+ case 5: return &op_fltq_q;
1845
}
1846
break;
1847
case 89:
1848
switch (((inst >> 12) & 0b111)) {
1881
- case 0: op = rv_op_fmvp_d_x; break;
1849
+ case 0: return &op_fmvp_d_x;
1850
}
1851
break;
1852
case 91:
1853
switch (((inst >> 12) & 0b111)) {
1886
- case 0: op = rv_op_fmvp_q_x; break;
1854
+ case 0: return &op_fmvp_q_x;
1855
}
1856
break;
1857
case 96:
1858
switch ((inst >> 20) & 0b11111) {
1891
- case 0: op = rv_op_fcvt_w_s; break;
1892
- case 1: op = rv_op_fcvt_wu_s; break;
1893
- case 2: op = rv_op_fcvt_l_s; break;
1894
- case 3: op = rv_op_fcvt_lu_s; break;
1859
+ case 0: return &op_fcvt_w_s;
1860
+ case 1: return &op_fcvt_wu_s;
1861
+ case 2: return &op_fcvt_l_s;
1862
+ case 3: return &op_fcvt_lu_s;
1863
}
1864
break;
1865
case 97:
1866
switch ((inst >> 20) & 0b11111) {
1899
- case 0: op = rv_op_fcvt_w_d; break;
1900
- case 1: op = rv_op_fcvt_wu_d; break;
1901
- case 2: op = rv_op_fcvt_l_d; break;
1902
- case 3: op = rv_op_fcvt_lu_d; break;
1903
- case 8: op = rv_op_fcvtmod_w_d; break;
1867
+ case 0: return &op_fcvt_w_d;
1868
+ case 1: return &op_fcvt_wu_d;
1869
+ case 2: return &op_fcvt_l_d;
1870
+ case 3: return &op_fcvt_lu_d;
1871
+ case 8: return &op_fcvtmod_w_d;
1872
}
1873
break;
1874
case 99:
1875
switch ((inst >> 20) & 0b11111) {
1908
- case 0: op = rv_op_fcvt_w_q; break;
1909
- case 1: op = rv_op_fcvt_wu_q; break;
1910
- case 2: op = rv_op_fcvt_l_q; break;
1911
- case 3: op = rv_op_fcvt_lu_q; break;
1876
+ case 0: return &op_fcvt_w_q;
1877
+ case 1: return &op_fcvt_wu_q;
1878
+ case 2: return &op_fcvt_l_q;
1879
+ case 3: return &op_fcvt_lu_q;
1880
}
1881
break;
1882
case 104:
1883
switch ((inst >> 20) & 0b11111) {
1916
- case 0: op = rv_op_fcvt_s_w; break;
1917
- case 1: op = rv_op_fcvt_s_wu; break;
1918
- case 2: op = rv_op_fcvt_s_l; break;
1919
- case 3: op = rv_op_fcvt_s_lu; break;
1884
+ case 0: return &op_fcvt_s_w;
1885
+ case 1: return &op_fcvt_s_wu;
1886
+ case 2: return &op_fcvt_s_l;
1887
+ case 3: return &op_fcvt_s_lu;
1888
}
1889
break;
1890
case 105:
1891
switch ((inst >> 20) & 0b11111) {
1924
- case 0: op = rv_op_fcvt_d_w; break;
1925
- case 1: op = rv_op_fcvt_d_wu; break;
1926
- case 2: op = rv_op_fcvt_d_l; break;
1927
- case 3: op = rv_op_fcvt_d_lu; break;
1892
+ case 0: return &op_fcvt_d_w;
1893
+ case 1: return &op_fcvt_d_wu;
1894
+ case 2: return &op_fcvt_d_l;
1895
+ case 3: return &op_fcvt_d_lu;
1896
}
1897
break;
1898
case 107:
1899
switch ((inst >> 20) & 0b11111) {
1932
- case 0: op = rv_op_fcvt_q_w; break;
1933
- case 1: op = rv_op_fcvt_q_wu; break;
1934
- case 2: op = rv_op_fcvt_q_l; break;
1935
- case 3: op = rv_op_fcvt_q_lu; break;
1900
+ case 0: return &op_fcvt_q_w;
1901
+ case 1: return &op_fcvt_q_wu;
1902
+ case 2: return &op_fcvt_q_l;
1903
+ case 3: return &op_fcvt_q_lu;
1904
}
1905
break;
1906
case 112:
1907
switch (((inst >> 17) & 0b11111000) |
1908
((inst >> 12) & 0b00000111)) {
1941
- case 0: op = rv_op_fmv_x_s; break;
1942
- case 1: op = rv_op_fclass_s; break;
1909
+ case 0: return &op_fmv_x_s;
1910
+ case 1: return &op_fclass_s;
1911
}
1912
break;
1913
case 113:
1914
switch (((inst >> 17) & 0b11111000) |
1915
((inst >> 12) & 0b00000111)) {
1948
- case 0: op = rv_op_fmv_x_d; break;
1949
- case 1: op = rv_op_fclass_d; break;
1950
- case 8: op = rv_op_fmvh_x_d; break;
1916
+ case 0: return &op_fmv_x_d;
1917
+ case 1: return &op_fclass_d;
1918
+ case 8: return &op_fmvh_x_d;
1919
}
1920
break;
1921
case 114:
1922
switch (((inst >> 17) & 0b11111000) |
1923
((inst >> 12) & 0b00000111)) {
1956
- case 0: op = rv_op_fmv_x_h; break;
1924
+ case 0: return &op_fmv_x_h;
1925
}
1926
break;
1927
case 115:
1928
switch (((inst >> 17) & 0b11111000) |
1929
((inst >> 12) & 0b00000111)) {
1962
- case 0: op = rv_op_fmv_x_q; break;
1963
- case 1: op = rv_op_fclass_q; break;
1964
- case 8: op = rv_op_fmvh_x_q; break;
1930
+ case 0: return &op_fmv_x_q;
1931
+ case 1: return &op_fclass_q;
1932
+ case 8: return &op_fmvh_x_q;
1933
}
1934
break;
1935
case 120:
1936
switch (((inst >> 17) & 0b11111000) |
1937
((inst >> 12) & 0b00000111)) {
1970
- case 0: op = rv_op_fmv_s_x; break;
1971
- case 8: op = rv_op_fli_s; break;
1938
+ case 0: return &op_fmv_s_x;
1939
+ case 8: return &op_fli_s;
1940
}
1941
break;
1942
case 121:
1943
switch (((inst >> 17) & 0b11111000) |
1944
((inst >> 12) & 0b00000111)) {
1977
- case 0: op = rv_op_fmv_d_x; break;
1978
- case 8: op = rv_op_fli_d; break;
1945
+ case 0: return &op_fmv_d_x;
1946
+ case 8: return &op_fli_d;
1947
}
1948
break;
1949
case 122:
1950
switch (((inst >> 17) & 0b11111000) |
1951
((inst >> 12) & 0b00000111)) {
1984
- case 0: op = rv_op_fmv_h_x; break;
1985
- case 8: op = rv_op_fli_h; break;
1952
+ case 0: return &op_fmv_h_x;
1953
+ case 8: return &op_fli_h;
1954
}
1955
break;
1956
case 123:
1957
switch (((inst >> 17) & 0b11111000) |
1958
((inst >> 12) & 0b00000111)) {
1991
- case 0: op = rv_op_fmv_q_x; break;
1992
- case 8: op = rv_op_fli_q; break;
1959
+ case 0: return &op_fmv_q_x;
1960
+ case 8: return &op_fli_q;
1961
}
1962
break;
1963
}
@@ -1998,484 +1966,537 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
1966
switch ((inst >> 12) & 0b111) {
1967
case 0:
1968
switch ((inst >> 26) & 0b111111) {
2001
- case 0: op = rv_op_vadd_vv; break;
2002
- case 1: op = rv_op_vandn_vv; break;
2003
- case 2: op = rv_op_vsub_vv; break;
2004
- case 4: op = rv_op_vminu_vv; break;
2005
- case 5: op = rv_op_vmin_vv; break;
2006
- case 6: op = rv_op_vmaxu_vv; break;
2007
- case 7: op = rv_op_vmax_vv; break;
2008
- case 9: op = rv_op_vand_vv; break;
2009
- case 10: op = rv_op_vor_vv; break;
2010
- case 11: op = rv_op_vxor_vv; break;
2011
- case 12: op = rv_op_vrgather_vv; break;
2012
- case 14: op = rv_op_vrgatherei16_vv; break;
1969
+ case 0: return &op_vadd_vv;
1970
+ case 1: return &op_vandn_vv;
1971
+ case 2: return &op_vsub_vv;
1972
+ case 4: return &op_vminu_vv;
1973
+ case 5: return &op_vmin_vv;
1974
+ case 6: return &op_vmaxu_vv;
1975
+ case 7: return &op_vmax_vv;
1976
+ case 9: return &op_vand_vv;
1977
+ case 10: return &op_vor_vv;
1978
+ case 11: return &op_vxor_vv;
1979
+ case 12: return &op_vrgather_vv;
1980
+ case 14: return &op_vrgatherei16_vv;
1981
case 16:
1982
if (((inst >> 25) & 1) == 0) {
2015
- op = rv_op_vadc_vvm;
1983
+ return &op_vadc_vvm;
1984
}
1985
break;
2018
- case 17: op = rv_op_vmadc_vvm; break;
1986
+ case 17: return &op_vmadc_vvm;
1987
case 18:
1988
if (((inst >> 25) & 1) == 0) {
2021
- op = rv_op_vsbc_vvm;
1989
+ return &op_vsbc_vvm;
1990
}
1991
break;
2024
- case 19: op = rv_op_vmsbc_vvm; break;
2025
- case 20: op = rv_op_vror_vv; break;
2026
- case 21: op = rv_op_vrol_vv; break;
1992
+ case 19: return &op_vmsbc_vvm;
1993
+ case 20: return &op_vror_vv;
1994
+ case 21: return &op_vrol_vv;
1995
case 23:
2028
- if (((inst >> 20) & 0b111111) == 32)
2029
- op = rv_op_vmv_v_v;
2030
- else if (((inst >> 25) & 1) == 0)
2031
- op = rv_op_vmerge_vvm;
1996
+ if (((inst >> 20) & 0b111111) == 32) {
1997
+ return &op_vmv_v_v;
1998
+ } else if (((inst >> 25) & 1) == 0) {
1999
+ return &op_vmerge_vvm;
2000
+ }
2001
break;
2033
- case 24: op = rv_op_vmseq_vv; break;
2034
- case 25: op = rv_op_vmsne_vv; break;
2035
- case 26: op = rv_op_vmsltu_vv; break;
2036
- case 27: op = rv_op_vmslt_vv; break;
2037
- case 28: op = rv_op_vmsleu_vv; break;
2038
- case 29: op = rv_op_vmsle_vv; break;
2039
- case 32: op = rv_op_vsaddu_vv; break;
2040
- case 33: op = rv_op_vsadd_vv; break;
2041
- case 34: op = rv_op_vssubu_vv; break;
2042
- case 35: op = rv_op_vssub_vv; break;
2043
- case 37: op = rv_op_vsll_vv; break;
2044
- case 39: op = rv_op_vsmul_vv; break;
2045
- case 40: op = rv_op_vsrl_vv; break;
2046
- case 41: op = rv_op_vsra_vv; break;
2047
- case 42: op = rv_op_vssrl_vv; break;
2048
- case 43: op = rv_op_vssra_vv; break;
2049
- case 44: op = rv_op_vnsrl_wv; break;
2050
- case 45: op = rv_op_vnsra_wv; break;
2051
- case 46: op = rv_op_vnclipu_wv; break;
2052
- case 47: op = rv_op_vnclip_wv; break;
2053
- case 48: op = rv_op_vwredsumu_vs; break;
2054
- case 49: op = rv_op_vwredsum_vs; break;
2055
- case 53: op = rv_op_vwsll_vv; break;
2002
+ case 24: return &op_vmseq_vv;
2003
+ case 25: return &op_vmsne_vv;
2004
+ case 26: return &op_vmsltu_vv;
2005
+ case 27: return &op_vmslt_vv;
2006
+ case 28: return &op_vmsleu_vv;
2007
+ case 29: return &op_vmsle_vv;
2008
+ case 32: return &op_vsaddu_vv;
2009
+ case 33: return &op_vsadd_vv;
2010
+ case 34: return &op_vssubu_vv;
2011
+ case 35: return &op_vssub_vv;
2012
+ case 37: return &op_vsll_vv;
2013
+ case 39: return &op_vsmul_vv;
2014
+ case 40: return &op_vsrl_vv;
2015
+ case 41: return &op_vsra_vv;
2016
+ case 42: return &op_vssrl_vv;
2017
+ case 43: return &op_vssra_vv;
2018
+ case 44: return &op_vnsrl_wv;
2019
+ case 45: return &op_vnsra_wv;
2020
+ case 46: return &op_vnclipu_wv;
2021
+ case 47: return &op_vnclip_wv;
2022
+ case 48: return &op_vwredsumu_vs;
2023
+ case 49: return &op_vwredsum_vs;
2024
+ case 53: return &op_vwsll_vv;
2025
}
2026
break;
2027
case 1:
2028
switch ((inst >> 26) & 0b111111) {
2060
- case 0: op = rv_op_vfadd_vv; break;
2061
- case 1: op = rv_op_vfredusum_vs; break;
2062
- case 2: op = rv_op_vfsub_vv; break;
2063
- case 3: op = rv_op_vfredosum_vs; break;
2064
- case 4: op = rv_op_vfmin_vv; break;
2065
- case 5: op = rv_op_vfredmin_vs; break;
2066
- case 6: op = rv_op_vfmax_vv; break;
2067
- case 7: op = rv_op_vfredmax_vs; break;
2068
- case 8: op = rv_op_vfsgnj_vv; break;
2069
- case 9: op = rv_op_vfsgnjn_vv; break;
2070
- case 10: op = rv_op_vfsgnjx_vv; break;
2029
+ case 0: return &op_vfadd_vv;
2030
+ case 1: return &op_vfredusum_vs;
2031
+ case 2: return &op_vfsub_vv;
2032
+ case 3: return &op_vfredosum_vs;
2033
+ case 4: return &op_vfmin_vv;
2034
+ case 5: return &op_vfredmin_vs;
2035
+ case 6: return &op_vfmax_vv;
2036
+ case 7: return &op_vfredmax_vs;
2037
+ case 8: return &op_vfsgnj_vv;
2038
+ case 9: return &op_vfsgnjn_vv;
2039
+ case 10: return &op_vfsgnjx_vv;
2040
case 16:
2041
switch ((inst >> 15) & 0b11111) {
2073
- case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
2042
+ case 0:
2043
+ if ((inst >> 25) & 1) {
2044
+ return &op_vfmv_f_s;
2045
+ }
2046
}
2047
break;
2048
case 18:
2049
switch ((inst >> 15) & 0b11111) {
2078
- case 0: op = rv_op_vfcvt_xu_f_v; break;
2079
- case 1: op = rv_op_vfcvt_x_f_v; break;
2080
- case 2: op = rv_op_vfcvt_f_xu_v; break;
2081
- case 3: op = rv_op_vfcvt_f_x_v; break;
2082
- case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
2083
- case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
2084
- case 8: op = rv_op_vfwcvt_xu_f_v; break;
2085
- case 9: op = rv_op_vfwcvt_x_f_v; break;
2086
- case 10: op = rv_op_vfwcvt_f_xu_v; break;
2087
- case 11: op = rv_op_vfwcvt_f_x_v; break;
2088
- case 12: op = rv_op_vfwcvt_f_f_v; break;
2089
- case 13: op = rv_op_vfwcvtbf16_f_f_v; break;
2090
- case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
2091
- case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
2092
- case 16: op = rv_op_vfncvt_xu_f_w; break;
2093
- case 17: op = rv_op_vfncvt_x_f_w; break;
2094
- case 18: op = rv_op_vfncvt_f_xu_w; break;
2095
- case 19: op = rv_op_vfncvt_f_x_w; break;
2096
- case 20: op = rv_op_vfncvt_f_f_w; break;
2097
- case 21: op = rv_op_vfncvt_rod_f_f_w; break;
2098
- case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
2099
- case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
2100
- case 29: op = rv_op_vfncvtbf16_f_f_w; break;
2050
+ case 0: return &op_vfcvt_xu_f_v;
2051
+ case 1: return &op_vfcvt_x_f_v;
2052
+ case 2: return &op_vfcvt_f_xu_v;
2053
+ case 3: return &op_vfcvt_f_x_v;
2054
+ case 6: return &op_vfcvt_rtz_xu_f_v;
2055
+ case 7: return &op_vfcvt_rtz_x_f_v;
2056
+ case 8: return &op_vfwcvt_xu_f_v;
2057
+ case 9: return &op_vfwcvt_x_f_v;
2058
+ case 10: return &op_vfwcvt_f_xu_v;
2059
+ case 11: return &op_vfwcvt_f_x_v;
2060
+ case 12: return &op_vfwcvt_f_f_v;
2061
+ case 13: return &op_vfwcvtbf16_f_f_v;
2062
+ case 14: return &op_vfwcvt_rtz_xu_f_v;
2063
+ case 15: return &op_vfwcvt_rtz_x_f_v;
2064
+ case 16: return &op_vfncvt_xu_f_w;
2065
+ case 17: return &op_vfncvt_x_f_w;
2066
+ case 18: return &op_vfncvt_f_xu_w;
2067
+ case 19: return &op_vfncvt_f_x_w;
2068
+ case 20: return &op_vfncvt_f_f_w;
2069
+ case 21: return &op_vfncvt_rod_f_f_w;
2070
+ case 22: return &op_vfncvt_rtz_xu_f_w;
2071
+ case 23: return &op_vfncvt_rtz_x_f_w;
2072
+ case 29: return &op_vfncvtbf16_f_f_w;
2073
}
2074
break;
2075
case 19:
2076
switch ((inst >> 15) & 0b11111) {
2105
- case 0: op = rv_op_vfsqrt_v; break;
2106
- case 4: op = rv_op_vfrsqrt7_v; break;
2107
- case 5: op = rv_op_vfrec7_v; break;
2108
- case 16: op = rv_op_vfclass_v; break;
2077
+ case 0: return &op_vfsqrt_v;
2078
+ case 4: return &op_vfrsqrt7_v;
2079
+ case 5: return &op_vfrec7_v;
2080
+ case 16: return &op_vfclass_v;
2081
}
2082
break;
2111
- case 24: op = rv_op_vmfeq_vv; break;
2112
- case 25: op = rv_op_vmfle_vv; break;
2113
- case 27: op = rv_op_vmflt_vv; break;
2114
- case 28: op = rv_op_vmfne_vv; break;
2115
- case 32: op = rv_op_vfdiv_vv; break;
2116
- case 36: op = rv_op_vfmul_vv; break;
2117
- case 40: op = rv_op_vfmadd_vv; break;
2118
- case 41: op = rv_op_vfnmadd_vv; break;
2119
- case 42: op = rv_op_vfmsub_vv; break;
2120
- case 43: op = rv_op_vfnmsub_vv; break;
2121
- case 44: op = rv_op_vfmacc_vv; break;
2122
- case 45: op = rv_op_vfnmacc_vv; break;
2123
- case 46: op = rv_op_vfmsac_vv; break;
2124
- case 47: op = rv_op_vfnmsac_vv; break;
2125
- case 48: op = rv_op_vfwadd_vv; break;
2126
- case 49: op = rv_op_vfwredusum_vs; break;
2127
- case 50: op = rv_op_vfwsub_vv; break;
2128
- case 51: op = rv_op_vfwredosum_vs; break;
2129
- case 52: op = rv_op_vfwadd_wv; break;
2130
- case 54: op = rv_op_vfwsub_wv; break;
2131
- case 56: op = rv_op_vfwmul_vv; break;
2132
- case 59: op = rv_op_vfwmaccbf16_vv; break;
2133
- case 60: op = rv_op_vfwmacc_vv; break;
2134
- case 61: op = rv_op_vfwnmacc_vv; break;
2135
- case 62: op = rv_op_vfwmsac_vv; break;
2136
- case 63: op = rv_op_vfwnmsac_vv; break;
2083
+ case 24: return &op_vmfeq_vv;
2084
+ case 25: return &op_vmfle_vv;
2085
+ case 27: return &op_vmflt_vv;
2086
+ case 28: return &op_vmfne_vv;
2087
+ case 32: return &op_vfdiv_vv;
2088
+ case 36: return &op_vfmul_vv;
2089
+ case 40: return &op_vfmadd_vv;
2090
+ case 41: return &op_vfnmadd_vv;
2091
+ case 42: return &op_vfmsub_vv;
2092
+ case 43: return &op_vfnmsub_vv;
2093
+ case 44: return &op_vfmacc_vv;
2094
+ case 45: return &op_vfnmacc_vv;
2095
+ case 46: return &op_vfmsac_vv;
2096
+ case 47: return &op_vfnmsac_vv;
2097
+ case 48: return &op_vfwadd_vv;
2098
+ case 49: return &op_vfwredusum_vs;
2099
+ case 50: return &op_vfwsub_vv;
2100
+ case 51: return &op_vfwredosum_vs;
2101
+ case 52: return &op_vfwadd_wv;
2102
+ case 54: return &op_vfwsub_wv;
2103
+ case 56: return &op_vfwmul_vv;
2104
+ case 59: return &op_vfwmaccbf16_vv;
2105
+ case 60: return &op_vfwmacc_vv;
2106
+ case 61: return &op_vfwnmacc_vv;
2107
+ case 62: return &op_vfwmsac_vv;
2108
+ case 63: return &op_vfwnmsac_vv;
2109
}
2110
break;
2111
case 2:
2112
switch ((inst >> 26) & 0b111111) {
2141
- case 0: op = rv_op_vredsum_vs; break;
2142
- case 1: op = rv_op_vredand_vs; break;
2143
- case 2: op = rv_op_vredor_vs; break;
2144
- case 3: op = rv_op_vredxor_vs; break;
2145
- case 4: op = rv_op_vredminu_vs; break;
2146
- case 5: op = rv_op_vredmin_vs; break;
2147
- case 6: op = rv_op_vredmaxu_vs; break;
2148
- case 7: op = rv_op_vredmax_vs; break;
2149
- case 8: op = rv_op_vaaddu_vv; break;
2150
- case 9: op = rv_op_vaadd_vv; break;
2151
- case 10: op = rv_op_vasubu_vv; break;
2152
- case 11: op = rv_op_vasub_vv; break;
2153
- case 12: op = rv_op_vclmul_vv; break;
2154
- case 13: op = rv_op_vclmulh_vv; break;
2113
+ case 0: return &op_vredsum_vs;
2114
+ case 1: return &op_vredand_vs;
2115
+ case 2: return &op_vredor_vs;
2116
+ case 3: return &op_vredxor_vs;
2117
+ case 4: return &op_vredminu_vs;
2118
+ case 5: return &op_vredmin_vs;
2119
+ case 6: return &op_vredmaxu_vs;
2120
+ case 7: return &op_vredmax_vs;
2121
+ case 8: return &op_vaaddu_vv;
2122
+ case 9: return &op_vaadd_vv;
2123
+ case 10: return &op_vasubu_vv;
2124
+ case 11: return &op_vasub_vv;
2125
+ case 12: return &op_vclmul_vv;
2126
+ case 13: return &op_vclmulh_vv;
2127
case 16:
2128
switch ((inst >> 15) & 0b11111) {
2157
- case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
2158
- case 16: op = rv_op_vcpop_m; break;
2159
- case 17: op = rv_op_vfirst_m; break;
2129
+ case 0:
2130
+ if ((inst >> 25) & 1) {
2131
+ return &op_vmv_x_s;
2132
+ }
2133
+ break;
2134
+ case 16: return &op_vcpop_m;
2135
+ case 17: return &op_vfirst_m;
2136
}
2137
break;
2138
case 18:
2139
switch ((inst >> 15) & 0b11111) {
2164
- case 2: op = rv_op_vzext_vf8; break;
2165
- case 3: op = rv_op_vsext_vf8; break;
2166
- case 4: op = rv_op_vzext_vf4; break;
2167
- case 5: op = rv_op_vsext_vf4; break;
2168
- case 6: op = rv_op_vzext_vf2; break;
2169
- case 7: op = rv_op_vsext_vf2; break;
2170
- case 8: op = rv_op_vbrev8_v; break;
2171
- case 9: op = rv_op_vrev8_v; break;
2172
- case 10: op = rv_op_vbrev_v; break;
2173
- case 12: op = rv_op_vclz_v; break;
2174
- case 13: op = rv_op_vctz_v; break;
2175
- case 14: op = rv_op_vcpop_v; break;
2140
+ case 2: return &op_vzext_vf8;
2141
+ case 3: return &op_vsext_vf8;
2142
+ case 4: return &op_vzext_vf4;
2143
+ case 5: return &op_vsext_vf4;
2144
+ case 6: return &op_vzext_vf2;
2145
+ case 7: return &op_vsext_vf2;
2146
+ case 8: return &op_vbrev8_v;
2147
+ case 9: return &op_vrev8_v;
2148
+ case 10: return &op_vbrev_v;
2149
+ case 12: return &op_vclz_v;
2150
+ case 13: return &op_vctz_v;
2151
+ case 14: return &op_vcpop_v;
2152
}
2153
break;
2154
case 20:
2155
switch ((inst >> 15) & 0b11111) {
2180
- case 1: op = rv_op_vmsbf_m; break;
2181
- case 2: op = rv_op_vmsof_m; break;
2182
- case 3: op = rv_op_vmsif_m; break;
2183
- case 16: op = rv_op_viota_m; break;
2156
+ case 1: return &op_vmsbf_m; break;
2157
+ case 2: return &op_vmsof_m;
2158
+ case 3: return &op_vmsif_m;
2159
+ case 16: return &op_viota_m;
2160
case 17:
2161
if (((inst >> 20) & 0b11111) == 0) {
2186
- op = rv_op_vid_v;
2162
+ return &op_vid_v;
2163
}
2164
break;
2165
}
2166
break;
2191
- case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
2192
- case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
2193
- case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
2194
- case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
2195
- case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
2196
- case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
2197
- case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
2198
- case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
2199
- case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
2200
- case 32: op = rv_op_vdivu_vv; break;
2201
- case 33: op = rv_op_vdiv_vv; break;
2202
- case 34: op = rv_op_vremu_vv; break;
2203
- case 35: op = rv_op_vrem_vv; break;
2204
- case 36: op = rv_op_vmulhu_vv; break;
2205
- case 37: op = rv_op_vmul_vv; break;
2206
- case 38: op = rv_op_vmulhsu_vv; break;
2207
- case 39: op = rv_op_vmulh_vv; break;
2208
- case 41: op = rv_op_vmadd_vv; break;
2209
- case 43: op = rv_op_vnmsub_vv; break;
2210
- case 45: op = rv_op_vmacc_vv; break;
2211
- case 47: op = rv_op_vnmsac_vv; break;
2212
- case 48: op = rv_op_vwaddu_vv; break;
2213
- case 49: op = rv_op_vwadd_vv; break;
2214
- case 50: op = rv_op_vwsubu_vv; break;
2215
- case 51: op = rv_op_vwsub_vv; break;
2216
- case 52: op = rv_op_vwaddu_wv; break;
2217
- case 53: op = rv_op_vwadd_wv; break;
2218
- case 54: op = rv_op_vwsubu_wv; break;
2219
- case 55: op = rv_op_vwsub_wv; break;
2220
- case 56: op = rv_op_vwmulu_vv; break;
2221
- case 58: op = rv_op_vwmulsu_vv; break;
2222
- case 59: op = rv_op_vwmul_vv; break;
2223
- case 60: op = rv_op_vwmaccu_vv; break;
2224
- case 61: op = rv_op_vwmacc_vv; break;
2225
- case 63: op = rv_op_vwmaccsu_vv; break;
2167
+ case 23:
2168
+ if ((inst >> 25) & 1) {
2169
+ return &op_vcompress_vm;
2170
+ }
2171
+ break;
2172
+ case 24:
2173
+ if ((inst >> 25) & 1) {
2174
+ return &op_vmandn_mm;
2175
+ }
2176
+ break;
2177
+ case 25:
2178
+ if ((inst >> 25) & 1) {
2179
+ return &op_vmand_mm;
2180
+ }
2181
+ break;
2182
+ case 26:
2183
+ if ((inst >> 25) & 1) {
2184
+ return &op_vmor_mm;
2185
+ }
2186
+ break;
2187
+ case 27:
2188
+ if ((inst >> 25) & 1) {
2189
+ return &op_vmxor_mm;
2190
+ }
2191
+ break;
2192
+ case 28:
2193
+ if ((inst >> 25) & 1) {
2194
+ return &op_vmorn_mm;
2195
+ }
2196
+ break;
2197
+ case 29:
2198
+ if ((inst >> 25) & 1) {
2199
+ return &op_vmnand_mm;
2200
+ }
2201
+ break;
2202
+ case 30:
2203
+ if ((inst >> 25) & 1) {
2204
+ return &op_vmnor_mm;
2205
+ }
2206
+ break;
2207
+ case 31:
2208
+ if ((inst >> 25) & 1) {
2209
+ return &op_vmxnor_mm;
2210
+ }
2211
+ break;
2212
+ case 32: return &op_vdivu_vv;
2213
+ case 33: return &op_vdiv_vv;
2214
+ case 34: return &op_vremu_vv;
2215
+ case 35: return &op_vrem_vv;
2216
+ case 36: return &op_vmulhu_vv;
2217
+ case 37: return &op_vmul_vv;
2218
+ case 38: return &op_vmulhsu_vv;
2219
+ case 39: return &op_vmulh_vv;
2220
+ case 41: return &op_vmadd_vv;
2221
+ case 43: return &op_vnmsub_vv;
2222
+ case 45: return &op_vmacc_vv;
2223
+ case 47: return &op_vnmsac_vv;
2224
+ case 48: return &op_vwaddu_vv;
2225
+ case 49: return &op_vwadd_vv;
2226
+ case 50: return &op_vwsubu_vv;
2227
+ case 51: return &op_vwsub_vv;
2228
+ case 52: return &op_vwaddu_wv;
2229
+ case 53: return &op_vwadd_wv;
2230
+ case 54: return &op_vwsubu_wv;
2231
+ case 55: return &op_vwsub_wv;
2232
+ case 56: return &op_vwmulu_vv;
2233
+ case 58: return &op_vwmulsu_vv;
2234
+ case 59: return &op_vwmul_vv;
2235
+ case 60: return &op_vwmaccu_vv;
2236
+ case 61: return &op_vwmacc_vv;
2237
+ case 63: return &op_vwmaccsu_vv;
2238
}
2239
break;
2240
case 3:
2241
switch ((inst >> 26) & 0b111111) {
2230
- case 0: op = rv_op_vadd_vi; break;
2231
- case 3: op = rv_op_vrsub_vi; break;
2232
- case 9: op = rv_op_vand_vi; break;
2233
- case 10: op = rv_op_vor_vi; break;
2234
- case 11: op = rv_op_vxor_vi; break;
2235
- case 12: op = rv_op_vrgather_vi; break;
2236
- case 14: op = rv_op_vslideup_vi; break;
2237
- case 15: op = rv_op_vslidedown_vi; break;
2242
+ case 0: return &op_vadd_vi;
2243
+ case 3: return &op_vrsub_vi;
2244
+ case 9: return &op_vand_vi;
2245
+ case 10: return &op_vor_vi;
2246
+ case 11: return &op_vxor_vi;
2247
+ case 12: return &op_vrgather_vi;
2248
+ case 14: return &op_vslideup_vi;
2249
+ case 15: return &op_vslidedown_vi;
2250
case 16:
2251
if (((inst >> 25) & 1) == 0) {
2240
- op = rv_op_vadc_vim;
2252
+ return &op_vadc_vim;
2253
}
2254
break;
2243
- case 17: op = rv_op_vmadc_vim; break;
2244
- case 20: case 21: op = rv_op_vror_vi; break;
2255
+ case 17: return &op_vmadc_vim;
2256
+ case 20: case 21: return &op_vror_vi;
2257
case 23:
2246
- if (((inst >> 20) & 0b111111) == 32)
2247
- op = rv_op_vmv_v_i;
2248
- else if (((inst >> 25) & 1) == 0)
2249
- op = rv_op_vmerge_vim;
2258
+ if (((inst >> 20) & 0b111111) == 32) {
2259
+ return &op_vmv_v_i;
2260
+ } else if (((inst >> 25) & 1) == 0) {
2261
+ return &op_vmerge_vim;
2262
+ }
2263
break;
2251
- case 24: op = rv_op_vmseq_vi; break;
2252
- case 25: op = rv_op_vmsne_vi; break;
2253
- case 28: op = rv_op_vmsleu_vi; break;
2254
- case 29: op = rv_op_vmsle_vi; break;
2255
- case 30: op = rv_op_vmsgtu_vi; break;
2256
- case 31: op = rv_op_vmsgt_vi; break;
2257
- case 32: op = rv_op_vsaddu_vi; break;
2258
- case 33: op = rv_op_vsadd_vi; break;
2259
- case 37: op = rv_op_vsll_vi; break;
2264
+ case 24: return &op_vmseq_vi;
2265
+ case 25: return &op_vmsne_vi;
2266
+ case 28: return &op_vmsleu_vi;
2267
+ case 29: return &op_vmsle_vi;
2268
+ case 30: return &op_vmsgtu_vi;
2269
+ case 31: return &op_vmsgt_vi;
2270
+ case 32: return &op_vsaddu_vi;
2271
+ case 33: return &op_vsadd_vi;
2272
+ case 37: return &op_vsll_vi;
2273
case 39:
2274
switch ((inst >> 15) & 0b11111) {
2262
- case 0: op = rv_op_vmv1r_v; break;
2263
- case 1: op = rv_op_vmv2r_v; break;
2264
- case 3: op = rv_op_vmv4r_v; break;
2265
- case 7: op = rv_op_vmv8r_v; break;
2275
+ case 0: return &op_vmv1r_v;
2276
+ case 1: return &op_vmv2r_v;
2277
+ case 3: return &op_vmv4r_v;
2278
+ case 7: return &op_vmv8r_v;
2279
}
2280
break;
2268
- case 40: op = rv_op_vsrl_vi; break;
2269
- case 41: op = rv_op_vsra_vi; break;
2270
- case 42: op = rv_op_vssrl_vi; break;
2271
- case 43: op = rv_op_vssra_vi; break;
2272
- case 44: op = rv_op_vnsrl_wi; break;
2273
- case 45: op = rv_op_vnsra_wi; break;
2274
- case 46: op = rv_op_vnclipu_wi; break;
2275
- case 47: op = rv_op_vnclip_wi; break;
2276
- case 53: op = rv_op_vwsll_vi; break;
2281
+ case 40: return &op_vsrl_vi;
2282
+ case 41: return &op_vsra_vi;
2283
+ case 42: return &op_vssrl_vi;
2284
+ case 43: return &op_vssra_vi;
2285
+ case 44: return &op_vnsrl_wi;
2286
+ case 45: return &op_vnsra_wi;
2287
+ case 46: return &op_vnclipu_wi;
2288
+ case 47: return &op_vnclip_wi;
2289
+ case 53: return &op_vwsll_vi;
2290
}
2291
break;
2292
case 4:
2293
switch ((inst >> 26) & 0b111111) {
2281
- case 0: op = rv_op_vadd_vx; break;
2282
- case 1: op = rv_op_vandn_vx; break;
2283
- case 2: op = rv_op_vsub_vx; break;
2284
- case 3: op = rv_op_vrsub_vx; break;
2285
- case 4: op = rv_op_vminu_vx; break;
2286
- case 5: op = rv_op_vmin_vx; break;
2287
- case 6: op = rv_op_vmaxu_vx; break;
2288
- case 7: op = rv_op_vmax_vx; break;
2289
- case 9: op = rv_op_vand_vx; break;
2290
- case 10: op = rv_op_vor_vx; break;
2291
- case 11: op = rv_op_vxor_vx; break;
2292
- case 12: op = rv_op_vrgather_vx; break;
2293
- case 14: op = rv_op_vslideup_vx; break;
2294
- case 15: op = rv_op_vslidedown_vx; break;
2294
+ case 0: return &op_vadd_vx;
2295
+ case 1: return &op_vandn_vx;
2296
+ case 2: return &op_vsub_vx;
2297
+ case 3: return &op_vrsub_vx;
2298
+ case 4: return &op_vminu_vx;
2299
+ case 5: return &op_vmin_vx;
2300
+ case 6: return &op_vmaxu_vx;
2301
+ case 7: return &op_vmax_vx;
2302
+ case 9: return &op_vand_vx;
2303
+ case 10: return &op_vor_vx;
2304
+ case 11: return &op_vxor_vx;
2305
+ case 12: return &op_vrgather_vx;
2306
+ case 14: return &op_vslideup_vx;
2307
+ case 15: return &op_vslidedown_vx;
2308
case 16:
2309
if (((inst >> 25) & 1) == 0) {
2297
- op = rv_op_vadc_vxm;
2310
+ return &op_vadc_vxm;
2311
}
2312
break;
2300
- case 17: op = rv_op_vmadc_vxm; break;
2313
+ case 17: return &op_vmadc_vxm;
2314
case 18:
2315
if (((inst >> 25) & 1) == 0) {
2303
- op = rv_op_vsbc_vxm;
2316
+ return &op_vsbc_vxm;
2317
}
2318
break;
2306
- case 19: op = rv_op_vmsbc_vxm; break;
2307
- case 20: op = rv_op_vror_vx; break;
2308
- case 21: op = rv_op_vrol_vx; break;
2319
+ case 19: return &op_vmsbc_vxm;
2320
+ case 20: return &op_vror_vx;
2321
+ case 21: return &op_vrol_vx;
2322
case 23:
2310
- if (((inst >> 20) & 0b111111) == 32)
2311
- op = rv_op_vmv_v_x;
2312
- else if (((inst >> 25) & 1) == 0)
2313
- op = rv_op_vmerge_vxm;
2323
+ if (((inst >> 20) & 0b111111) == 32) {
2324
+ return &op_vmv_v_x;
2325
+ } else if (((inst >> 25) & 1) == 0) {
2326
+ return &op_vmerge_vxm;
2327
+ }
2328
break;
2315
- case 24: op = rv_op_vmseq_vx; break;
2316
- case 25: op = rv_op_vmsne_vx; break;
2317
- case 26: op = rv_op_vmsltu_vx; break;
2318
- case 27: op = rv_op_vmslt_vx; break;
2319
- case 28: op = rv_op_vmsleu_vx; break;
2320
- case 29: op = rv_op_vmsle_vx; break;
2321
- case 30: op = rv_op_vmsgtu_vx; break;
2322
- case 31: op = rv_op_vmsgt_vx; break;
2323
- case 32: op = rv_op_vsaddu_vx; break;
2324
- case 33: op = rv_op_vsadd_vx; break;
2325
- case 34: op = rv_op_vssubu_vx; break;
2326
- case 35: op = rv_op_vssub_vx; break;
2327
- case 37: op = rv_op_vsll_vx; break;
2328
- case 39: op = rv_op_vsmul_vx; break;
2329
- case 40: op = rv_op_vsrl_vx; break;
2330
- case 41: op = rv_op_vsra_vx; break;
2331
- case 42: op = rv_op_vssrl_vx; break;
2332
- case 43: op = rv_op_vssra_vx; break;
2333
- case 44: op = rv_op_vnsrl_wx; break;
2334
- case 45: op = rv_op_vnsra_wx; break;
2335
- case 46: op = rv_op_vnclipu_wx; break;
2336
- case 47: op = rv_op_vnclip_wx; break;
2337
- case 53: op = rv_op_vwsll_vx; break;
2329
+ case 24: return &op_vmseq_vx;
2330
+ case 25: return &op_vmsne_vx;
2331
+ case 26: return &op_vmsltu_vx;
2332
+ case 27: return &op_vmslt_vx;
2333
+ case 28: return &op_vmsleu_vx;
2334
+ case 29: return &op_vmsle_vx;
2335
+ case 30: return &op_vmsgtu_vx;
2336
+ case 31: return &op_vmsgt_vx;
2337
+ case 32: return &op_vsaddu_vx;
2338
+ case 33: return &op_vsadd_vx;
2339
+ case 34: return &op_vssubu_vx;
2340
+ case 35: return &op_vssub_vx;
2341
+ case 37: return &op_vsll_vx;
2342
+ case 39: return &op_vsmul_vx;
2343
+ case 40: return &op_vsrl_vx;
2344
+ case 41: return &op_vsra_vx;
2345
+ case 42: return &op_vssrl_vx;
2346
+ case 43: return &op_vssra_vx;
2347
+ case 44: return &op_vnsrl_wx;
2348
+ case 45: return &op_vnsra_wx;
2349
+ case 46: return &op_vnclipu_wx;
2350
+ case 47: return &op_vnclip_wx;
2351
+ case 53: return &op_vwsll_vx;
2352
}
2353
break;
2354
case 5:
2355
switch ((inst >> 26) & 0b111111) {
2342
- case 0: op = rv_op_vfadd_vf; break;
2343
- case 2: op = rv_op_vfsub_vf; break;
2344
- case 4: op = rv_op_vfmin_vf; break;
2345
- case 6: op = rv_op_vfmax_vf; break;
2346
- case 8: op = rv_op_vfsgnj_vf; break;
2347
- case 9: op = rv_op_vfsgnjn_vf; break;
2348
- case 10: op = rv_op_vfsgnjx_vf; break;
2349
- case 14: op = rv_op_vfslide1up_vf; break;
2350
- case 15: op = rv_op_vfslide1down_vf; break;
2356
+ case 0: return &op_vfadd_vf;
2357
+ case 2: return &op_vfsub_vf;
2358
+ case 4: return &op_vfmin_vf;
2359
+ case 6: return &op_vfmax_vf;
2360
+ case 8: return &op_vfsgnj_vf;
2361
+ case 9: return &op_vfsgnjn_vf;
2362
+ case 10: return &op_vfsgnjx_vf;
2363
+ case 14: return &op_vfslide1up_vf;
2364
+ case 15: return &op_vfslide1down_vf;
2365
case 16:
2366
switch ((inst >> 20) & 0b11111) {
2353
- case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
2367
+ case 0:
2368
+ if ((inst >> 25) & 1) {
2369
+ return &op_vfmv_s_f;
2370
+ }
2371
}
2372
break;
2373
case 23:
2357
- if (((inst >> 25) & 1) == 0)
2358
- op = rv_op_vfmerge_vfm;
2359
- else if (((inst >> 20) & 0b111111) == 32)
2360
- op = rv_op_vfmv_v_f;
2374
+ if (((inst >> 25) & 1) == 0) {
2375
+ return &op_vfmerge_vfm;
2376
+ } else if (((inst >> 20) & 0b111111) == 32) {
2377
+ return &op_vfmv_v_f;
2378
+ }
2379
break;
2362
- case 24: op = rv_op_vmfeq_vf; break;
2363
- case 25: op = rv_op_vmfle_vf; break;
2364
- case 27: op = rv_op_vmflt_vf; break;
2365
- case 28: op = rv_op_vmfne_vf; break;
2366
- case 29: op = rv_op_vmfgt_vf; break;
2367
- case 31: op = rv_op_vmfge_vf; break;
2368
- case 32: op = rv_op_vfdiv_vf; break;
2369
- case 33: op = rv_op_vfrdiv_vf; break;
2370
- case 36: op = rv_op_vfmul_vf; break;
2371
- case 39: op = rv_op_vfrsub_vf; break;
2372
- case 40: op = rv_op_vfmadd_vf; break;
2373
- case 41: op = rv_op_vfnmadd_vf; break;
2374
- case 42: op = rv_op_vfmsub_vf; break;
2375
- case 43: op = rv_op_vfnmsub_vf; break;
2376
- case 44: op = rv_op_vfmacc_vf; break;
2377
- case 45: op = rv_op_vfnmacc_vf; break;
2378
- case 46: op = rv_op_vfmsac_vf; break;
2379
- case 47: op = rv_op_vfnmsac_vf; break;
2380
- case 48: op = rv_op_vfwadd_vf; break;
2381
- case 50: op = rv_op_vfwsub_vf; break;
2382
- case 52: op = rv_op_vfwadd_wf; break;
2383
- case 54: op = rv_op_vfwsub_wf; break;
2384
- case 56: op = rv_op_vfwmul_vf; break;
2385
- case 59: op = rv_op_vfwmaccbf16_vf; break;
2386
- case 60: op = rv_op_vfwmacc_vf; break;
2387
- case 61: op = rv_op_vfwnmacc_vf; break;
2388
- case 62: op = rv_op_vfwmsac_vf; break;
2389
- case 63: op = rv_op_vfwnmsac_vf; break;
2380
+ case 24: return &op_vmfeq_vf;
2381
+ case 25: return &op_vmfle_vf;
2382
+ case 27: return &op_vmflt_vf;
2383
+ case 28: return &op_vmfne_vf;
2384
+ case 29: return &op_vmfgt_vf;
2385
+ case 31: return &op_vmfge_vf;
2386
+ case 32: return &op_vfdiv_vf;
2387
+ case 33: return &op_vfrdiv_vf;
2388
+ case 36: return &op_vfmul_vf;
2389
+ case 39: return &op_vfrsub_vf;
2390
+ case 40: return &op_vfmadd_vf;
2391
+ case 41: return &op_vfnmadd_vf;
2392
+ case 42: return &op_vfmsub_vf;
2393
+ case 43: return &op_vfnmsub_vf;
2394
+ case 44: return &op_vfmacc_vf;
2395
+ case 45: return &op_vfnmacc_vf;
2396
+ case 46: return &op_vfmsac_vf;
2397
+ case 47: return &op_vfnmsac_vf;
2398
+ case 48: return &op_vfwadd_vf;
2399
+ case 50: return &op_vfwsub_vf;
2400
+ case 52: return &op_vfwadd_wf;
2401
+ case 54: return &op_vfwsub_wf;
2402
+ case 56: return &op_vfwmul_vf;
2403
+ case 59: return &op_vfwmaccbf16_vf;
2404
+ case 60: return &op_vfwmacc_vf;
2405
+ case 61: return &op_vfwnmacc_vf;
2406
+ case 62: return &op_vfwmsac_vf;
2407
+ case 63: return &op_vfwnmsac_vf;
2408
}
2409
break;
2410
case 6:
2411
switch ((inst >> 26) & 0b111111) {
2394
- case 8: op = rv_op_vaaddu_vx; break;
2395
- case 9: op = rv_op_vaadd_vx; break;
2396
- case 10: op = rv_op_vasubu_vx; break;
2397
- case 11: op = rv_op_vasub_vx; break;
2398
- case 12: op = rv_op_vclmul_vx; break;
2399
- case 13: op = rv_op_vclmulh_vx; break;
2400
- case 14: op = rv_op_vslide1up_vx; break;
2401
- case 15: op = rv_op_vslide1down_vx; break;
2412
+ case 8: return &op_vaaddu_vx;
2413
+ case 9: return &op_vaadd_vx;
2414
+ case 10: return &op_vasubu_vx;
2415
+ case 11: return &op_vasub_vx;
2416
+ case 12: return &op_vclmul_vx;
2417
+ case 13: return &op_vclmulh_vx;
2418
+ case 14: return &op_vslide1up_vx;
2419
+ case 15: return &op_vslide1down_vx;
2420
case 16:
2421
switch ((inst >> 20) & 0b11111) {
2404
- case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
2422
+ case 0:
2423
+ if ((inst >> 25) & 1) {
2424
+ return &op_vmv_s_x;
2425
+ }
2426
}
2427
break;
2407
- case 32: op = rv_op_vdivu_vx; break;
2408
- case 33: op = rv_op_vdiv_vx; break;
2409
- case 34: op = rv_op_vremu_vx; break;
2410
- case 35: op = rv_op_vrem_vx; break;
2411
- case 36: op = rv_op_vmulhu_vx; break;
2412
- case 37: op = rv_op_vmul_vx; break;
2413
- case 38: op = rv_op_vmulhsu_vx; break;
2414
- case 39: op = rv_op_vmulh_vx; break;
2415
- case 41: op = rv_op_vmadd_vx; break;
2416
- case 43: op = rv_op_vnmsub_vx; break;
2417
- case 45: op = rv_op_vmacc_vx; break;
2418
- case 47: op = rv_op_vnmsac_vx; break;
2419
- case 48: op = rv_op_vwaddu_vx; break;
2420
- case 49: op = rv_op_vwadd_vx; break;
2421
- case 50: op = rv_op_vwsubu_vx; break;
2422
- case 51: op = rv_op_vwsub_vx; break;
2423
- case 52: op = rv_op_vwaddu_wx; break;
2424
- case 53: op = rv_op_vwadd_wx; break;
2425
- case 54: op = rv_op_vwsubu_wx; break;
2426
- case 55: op = rv_op_vwsub_wx; break;
2427
- case 56: op = rv_op_vwmulu_vx; break;
2428
- case 58: op = rv_op_vwmulsu_vx; break;
2429
- case 59: op = rv_op_vwmul_vx; break;
2430
- case 60: op = rv_op_vwmaccu_vx; break;
2431
- case 61: op = rv_op_vwmacc_vx; break;
2432
- case 62: op = rv_op_vwmaccus_vx; break;
2433
- case 63: op = rv_op_vwmaccsu_vx; break;
2428
+ case 32: return &op_vdivu_vx;
2429
+ case 33: return &op_vdiv_vx;
2430
+ case 34: return &op_vremu_vx;
2431
+ case 35: return &op_vrem_vx;
2432
+ case 36: return &op_vmulhu_vx;
2433
+ case 37: return &op_vmul_vx;
2434
+ case 38: return &op_vmulhsu_vx;
2435
+ case 39: return &op_vmulh_vx;
2436
+ case 41: return &op_vmadd_vx;
2437
+ case 43: return &op_vnmsub_vx;
2438
+ case 45: return &op_vmacc_vx;
2439
+ case 47: return &op_vnmsac_vx;
2440
+ case 48: return &op_vwaddu_vx;
2441
+ case 49: return &op_vwadd_vx;
2442
+ case 50: return &op_vwsubu_vx;
2443
+ case 51: return &op_vwsub_vx;
2444
+ case 52: return &op_vwaddu_wx;
2445
+ case 53: return &op_vwadd_wx;
2446
+ case 54: return &op_vwsubu_wx;
2447
+ case 55: return &op_vwsub_wx;
2448
+ case 56: return &op_vwmulu_vx;
2449
+ case 58: return &op_vwmulsu_vx;
2450
+ case 59: return &op_vwmul_vx;
2451
+ case 60: return &op_vwmaccu_vx;
2452
+ case 61: return &op_vwmacc_vx;
2453
+ case 62: return &op_vwmaccus_vx;
2454
+ case 63: return &op_vwmaccsu_vx;
2455
}
2456
break;
2457
case 7:
2458
if (((inst >> 31) & 1) == 0) {
2438
- op = rv_op_vsetvli;
2459
+ return &op_vsetvli;
2460
} else if ((inst >> 30) & 1) {
2440
- op = rv_op_vsetivli;
2461
+ return &op_vsetivli;
2462
} else if (((inst >> 25) & 0b11111) == 0) {
2442
- op = rv_op_vsetvl;
2463
+ return &op_vsetvl;
2464
}
2465
break;
2466
}
2467
break;
2468
case 22:
2469
switch ((inst >> 12) & 0b111) {
2449
- case 0: op = rv_op_addid; break;
2470
+ case 0: return &op_addid;
2471
case 1:
2472
switch ((inst >> 26) & 0b111111) {
2452
- case 0: op = rv_op_sllid; break;
2473
+ case 0: return &op_sllid;
2474
}
2475
break;
2476
case 5:
2477
switch ((inst >> 26) & 0b111111) {
2457
- case 0: op = rv_op_srlid; break;
2458
- case 16: op = rv_op_sraid; break;
2478
+ case 0: return &op_srlid;
2479
+ case 16: return &op_sraid;
2480
}
2481
break;
2482
}
2483
break;
2484
case 24:
2485
switch ((inst >> 12) & 0b111) {
2465
- case 0: op = rv_op_beq; break;
2466
- case 1: op = rv_op_bne; break;
2467
- case 4: op = rv_op_blt; break;
2468
- case 5: op = rv_op_bge; break;
2469
- case 6: op = rv_op_bltu; break;
2470
- case 7: op = rv_op_bgeu; break;
2486
+ case 0: return &op_beq;
2487
+ case 1: return &op_bne;
2488
+ case 4: return &op_blt;
2489
+ case 5: return &op_bge;
2490
+ case 6: return &op_bltu;
2491
+ case 7: return &op_bgeu;
2492
}
2493
break;
2494
case 25:
2495
switch ((inst >> 12) & 0b111) {
2475
- case 0: op = rv_op_jalr; break;
2496
+ case 0: return &op_jalr;
2497
}
2498
break;
2478
- case 27: op = rv_op_jal; break;
2499
+ case 27: return &op_jal;
2500
case 28:
2501
switch ((inst >> 12) & 0b111) {
2502
case 0:
@@ -2483,76 +2504,76 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
2504
((inst >> 7) & 0b000000011111)) {
2505
case 0:
2506
switch ((inst >> 15) & 0b1111111111) {
2486
- case 0: op = rv_op_ecall; break;
2487
- case 32: op = rv_op_ebreak; break;
2488
- case 64: op = rv_op_uret; break;
2489
- case 416: op = rv_op_wrs_nto; break;
2490
- case 928: op = rv_op_wrs_sto; break;
2507
+ case 0: return &op_ecall;
2508
+ case 32: return &op_ebreak;
2509
+ case 64: return &op_uret;
2510
+ case 416: return &op_wrs_nto;
2511
+ case 928: return &op_wrs_sto;
2512
}
2513
break;
2514
case 256:
2515
switch ((inst >> 20) & 0b11111) {
2516
case 2:
2517
switch ((inst >> 15) & 0b11111) {
2497
- case 0: op = rv_op_sret; break;
2518
+ case 0: return &op_sret;
2519
}
2520
break;
2500
- case 4: op = rv_op_sfence_vm; break;
2521
+ case 4: return &op_sfence_vm;
2522
case 5:
2523
switch ((inst >> 15) & 0b11111) {
2503
- case 0: op = rv_op_wfi; break;
2524
+ case 0: return &op_wfi;
2525
}
2526
break;
2527
}
2528
break;
2508
- case 288: op = rv_op_sfence_vma; break;
2529
+ case 288: return &op_sfence_vma;
2530
case 512:
2531
switch ((inst >> 15) & 0b1111111111) {
2511
- case 64: op = rv_op_hret; break;
2532
+ case 64: return &op_hret;
2533
}
2534
break;
2535
case 768:
2536
switch ((inst >> 15) & 0b1111111111) {
2516
- case 64: op = rv_op_mret; break;
2537
+ case 64: return &op_mret;
2538
}
2539
break;
2540
case 1792:
2541
switch ((inst >> 15) & 0b1111111111) {
2521
- case 64: op = rv_op_mnret; break;
2542
+ case 64: return &op_mnret;
2543
}
2544
break;
2545
case 1952:
2546
switch ((inst >> 15) & 0b1111111111) {
2526
- case 576: op = rv_op_dret; break;
2547
+ case 576: return &op_dret;
2548
}
2549
break;
2550
}
2551
break;
2552
case 1:
2553
switch (operand_csr12(inst)) {
2533
- case 1: op = rv_op_fsflags; break;
2534
- case 2: op = rv_op_fsrm; break;
2535
- case 3: op = rv_op_fscsr; break;
2536
- default: op = rv_op_csrrw; break;
2554
+ case 1: return &op_fsflags;
2555
+ case 2: return &op_fsrm;
2556
+ case 3: return &op_fscsr;
2557
+ default: return &op_csrrw;
2558
}
2559
break;
2560
case 2:
2540
- op = rv_op_csrrs;
2561
+ return &op_csrrs;
2562
if (operand_rs1(inst) == 0) {
2563
switch (operand_csr12(inst)) {
2543
- case 0x001: op = rv_op_frflags; break;
2544
- case 0x002: op = rv_op_frrm; break;
2545
- case 0x003: op = rv_op_frcsr; break;
2546
- case 0xc00: op = rv_op_rdcycle; break;
2547
- case 0xc01: op = rv_op_rdtime; break;
2548
- case 0xc02: op = rv_op_rdinstret; break;
2549
- case 0xc80: op = rv_op_rdcycleh; break;
2550
- case 0xc81: op = rv_op_rdtimeh; break;
2551
- case 0xc82: op = rv_op_rdinstreth; break;
2564
+ case 0x001: return &op_frflags;
2565
+ case 0x002: return &op_frrm;
2566
+ case 0x003: return &op_frcsr;
2567
+ case 0xc00: return &op_rdcycle;
2568
+ case 0xc01: return &op_rdtime;
2569
+ case 0xc02: return &op_rdinstret;
2570
+ case 0xc80: return &op_rdcycleh;
2571
+ case 0xc81: return &op_rdtimeh;
2572
+ case 0xc82: return &op_rdinstreth;
2573
}
2574
}
2575
break;
2555
- case 3: op = rv_op_csrrc; break;
2576
+ case 3: return &op_csrrc;
2577
case 4:
2578
if (dec->cfg && dec->cfg->ext_zimop) {
2579
if (((inst >> 22) & 0b1011001111) == 0b1000000111) {
@@ -2560,15 +2581,15 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
2581
&& operand_mop_r_imm(inst) == 28) {
2582
switch (operand_rs1(inst)) {
2583
case 0:
2563
- return &rvi_opcode_data[rv_op_ssrdp];
2584
+ return &op_ssrdp;
2585
case 1:
2586
case 5:
2587
if (operand_rd(inst) == 0) {
2567
- return &rvi_opcode_data[rv_op_sspopchk];
2588
+ return &op_sspopchk;
2589
}
2590
}
2591
}
2571
- return &rvi_opcode_data[rv_op_mop_r];
2592
+ return &op_mop_r;
2593
}
2594
if (((inst >> 25) & 0b1011001) == 0b1000001) {
2595
if (dec->cfg->ext_zicfiss
@@ -2578,79 +2599,79 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
2599
switch (operand_rs2(inst)) {
2600
case 1:
2601
case 5:
2581
- return &rvi_opcode_data[rv_op_sspush];
2602
+ return &op_sspush;
2603
}
2604
}
2584
- return &rvi_opcode_data[rv_op_mop_rr];
2605
+ return &op_mop_rr;
2606
}
2607
}
2608
break;
2609
case 5:
2610
switch (operand_csr12(inst)) {
2590
- case 1: op = rv_op_fsflagsi; break;
2591
- case 2: op = rv_op_fsrmi; break;
2592
- default: op = rv_op_csrrwi; break;
2611
+ case 1: return &op_fsflagsi;
2612
+ case 2: return &op_fsrmi;
2613
+ default: return &op_csrrwi;
2614
}
2615
break;
2595
- case 6: op = rv_op_csrrsi; break;
2596
- case 7: op = rv_op_csrrci; break;
2616
+ case 6: return &op_csrrsi;
2617
+ case 7: return &op_csrrci;
2618
}
2619
break;
2620
case 29:
2621
if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
2622
switch ((inst >> 26) & 0b111111) {
2602
- case 32: op = rv_op_vsm3me_vv; break;
2603
- case 33: op = rv_op_vsm4k_vi; break;
2604
- case 34: op = rv_op_vaeskf1_vi; break;
2623
+ case 32: return &op_vsm3me_vv;
2624
+ case 33: return &op_vsm4k_vi;
2625
+ case 34: return &op_vaeskf1_vi;
2626
case 40:
2627
switch ((inst >> 15) & 0b11111) {
2607
- case 0: op = rv_op_vaesdm_vv; break;
2608
- case 1: op = rv_op_vaesdf_vv; break;
2609
- case 2: op = rv_op_vaesem_vv; break;
2610
- case 3: op = rv_op_vaesef_vv; break;
2611
- case 16: op = rv_op_vsm4r_vv; break;
2612
- case 17: op = rv_op_vgmul_vv; break;
2628
+ case 0: return &op_vaesdm_vv;
2629
+ case 1: return &op_vaesdf_vv;
2630
+ case 2: return &op_vaesem_vv;
2631
+ case 3: return &op_vaesef_vv;
2632
+ case 16: return &op_vsm4r_vv;
2633
+ case 17: return &op_vgmul_vv;
2634
}
2635
break;
2636
case 41:
2637
switch ((inst >> 15) & 0b11111) {
2617
- case 0: op = rv_op_vaesdm_vs; break;
2618
- case 1: op = rv_op_vaesdf_vs; break;
2619
- case 2: op = rv_op_vaesem_vs; break;
2620
- case 3: op = rv_op_vaesef_vs; break;
2621
- case 7: op = rv_op_vaesz_vs; break;
2622
- case 16: op = rv_op_vsm4r_vs; break;
2638
+ case 0: return &op_vaesdm_vs;
2639
+ case 1: return &op_vaesdf_vs;
2640
+ case 2: return &op_vaesem_vs;
2641
+ case 3: return &op_vaesef_vs;
2642
+ case 7: return &op_vaesz_vs;
2643
+ case 16: return &op_vsm4r_vs;
2644
}
2645
break;
2625
- case 42: op = rv_op_vaeskf2_vi; break;
2626
- case 43: op = rv_op_vsm3c_vi; break;
2627
- case 44: op = rv_op_vghsh_vv; break;
2628
- case 45: op = rv_op_vsha2ms_vv; break;
2629
- case 46: op = rv_op_vsha2ch_vv; break;
2630
- case 47: op = rv_op_vsha2cl_vv; break;
2646
+ case 42: return &op_vaeskf2_vi;
2647
+ case 43: return &op_vsm3c_vi;
2648
+ case 44: return &op_vghsh_vv;
2649
+ case 45: return &op_vsha2ms_vv;
2650
+ case 46: return &op_vsha2ch_vv;
2651
+ case 47: return &op_vsha2cl_vv;
2652
}
2653
}
2654
break;
2655
case 30:
2656
switch (((inst >> 22) & 0b1111111000) |
2657
((inst >> 12) & 0b0000000111)) {
2637
- case 0: op = rv_op_addd; break;
2638
- case 1: op = rv_op_slld; break;
2639
- case 5: op = rv_op_srld; break;
2640
- case 8: op = rv_op_muld; break;
2641
- case 12: op = rv_op_divd; break;
2642
- case 13: op = rv_op_divud; break;
2643
- case 14: op = rv_op_remd; break;
2644
- case 15: op = rv_op_remud; break;
2645
- case 256: op = rv_op_subd; break;
2646
- case 261: op = rv_op_srad; break;
2658
+ case 0: return &op_addd;
2659
+ case 1: return &op_slld;
2660
+ case 5: return &op_srld;
2661
+ case 8: return &op_muld;
2662
+ case 12: return &op_divd;
2663
+ case 13: return &op_divud;
2664
+ case 14: return &op_remd;
2665
+ case 15: return &op_remud;
2666
+ case 256: return &op_subd;
2667
+ case 261: return &op_srad;
2668
}
2669
break;
2670
}
2671
break;
2672
}
2673
2653
- return op == rv_op_illegal ? NULL : &rvi_opcode_data[op];
2674
+ return NULL;
2675
}
2676
2677
/* decode operands */
@@ -3450,7 +3471,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
3471
decode_inst_operands(&dec, isa, op);
3472
op = decode_inst_lift_pseudo(&dec, op);
3473
} else {
3453
- op = &rvi_opcode_data[rv_op_illegal];
3474
+ op = &op_illegal;
3475
}
3476
3477
return format_inst(24, &dec, op);