target/riscv: Fix seed CSR sign extension

The SEED_OPST_* macros expanded to int expressions. When bit 31 was present, converting a CSR seed value to target_ulong on RV64 sign extended the value and incorrectly set the upper 32 bits. Make the SEED_OPST_* constants unsigned so that CSR values are zero extended on RV64. Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/4121 Signed-off-by: Ivan Efremov <nendensu@ispras.ru> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260802113130.7818-2-nendensu@ispras.ru> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>