@samitouri / QOSamiQemu / commits / 517e357eea

hw/intc/gicv5: Define and use GICV5_PENDING_IRQ_NONE

The GICv5PendingIrq struct representation of "there is no pending interrupt" sets the prio field to PRIO_IDLE, and generally to avoid confusion we also set the intid to 0. We want to return this value or initialize some variable to it in several places in the GICv5 implementation, and the support for the virtual interrupt domain introduces more. Define a convenience macro for this special-case struct value, and use it instead of opencoding either the structure initializer or explicit assignment to the two fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-id: 20260615105029.2898872-6-peter.maydell@linaro.org

Peter Maydell committed Jun 15, 2026 at 11:50 UTC 517e357eeacd525eee2c95f91d47e35242cbdbe8

3 files changed +9 -8

hw/intc/arm_gicv5.c

+2 -4

@@ -429,8 +429,7 @@ static void irs_recalc_hppi(GICv5 *s, GICv5Domain domain, uint32_t iaffid)

429 ARMCPU *cpu = cpuidx >= 0 ? cs->cpus[cpuidx] : NULL;

430 GICv5PendingIrq best;

431

432 - best.intid = 0;

433 - best.prio = PRIO_IDLE;

432 + best = GICV5_PENDING_IRQ_NONE;

433

434 if (!cpu) {

435 /* Nothing happens for iaffids targeting nonexistent CPUs */

@@ -526,8 +525,7 @@ static void irs_recall_hppis(GICv5 *s, GICv5Domain domain)

525 GICv5Common *cs = ARM_GICV5_COMMON(s);

526

527 for (int i = 0; i < cs->num_cpus; i++) {

529 - s->hppi[domain][i].intid = 0;

530 - s->hppi[domain][i].prio = PRIO_IDLE;

528 + s->hppi[domain][i] = GICV5_PENDING_IRQ_NONE;

529 gicv5_forward_interrupt(cs->cpus[i], domain);

530 }

531 }

include/hw/intc/arm_gicv5_types.h

@@ -105,6 +105,10 @@ typedef struct GICv5PendingIrq {

105 uint8_t prio;

106 } GICv5PendingIrq;

107

108 +/* A GICv5PendingIrq struct initializer for "no pending interrupt" */

109 +#define GICV5_PENDING_IRQ_NONE \

110 + ((GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE })

111 +

112 /* Fields in a generic 32-bit INTID, per R_TJPHS */

113 FIELD(INTID, ID, 0, 24)

114 FIELD(INTID, TYPE, 29, 3)

target/arm/tcg/gicv5-cpuif.c

+3 -4

@@ -144,7 +144,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain)

144

145 if (!(env->gicv5_cpuif.icc_cr0[domain] & R_ICC_CR0_EN_MASK)) {

146 /* If cpuif is disabled there is no HPPI */

147 - return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE };

147 + return GICV5_PENDING_IRQ_NONE;

148 }

149

150 irs_hppi = gicv5_get_hppi(gic, domain, env->gicv5_iaffid);

@@ -168,7 +168,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain)

168 if (best.prio == PRIO_IDLE ||

169 best.prio > env->gicv5_cpuif.icc_pcr[domain] ||

170 best.prio >= gic_running_prio(env, domain)) {

171 - return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE };

171 + return GICV5_PENDING_IRQ_NONE;

172 }

173 return best;

174 }

@@ -258,8 +258,7 @@ static void gic_recalc_ppi_hppi(CPUARMState *env)

258 * enabled, pending and not active.

259 */

260 for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) {

261 - env->gicv5_cpuif.ppi_hppi[i].intid = 0;

262 - env->gicv5_cpuif.ppi_hppi[i].prio = PRIO_IDLE;

261 + env->gicv5_cpuif.ppi_hppi[i] = GICV5_PENDING_IRQ_NONE;

262 };

263

264 for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_active); i++) {