hw/hexagon: Add v68, sa8775-cdsp0 defs
Acked-by: Taylor Simpson <ltaylorsimpson@gmail.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jun 22, 2026 at 15:28 UTC
51e4b74c4cdec3300aeda70f1f5edf9524d2c68f
2 files changed
+128
hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc
new
+64
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+
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+static const struct hexagon_machine_config SA8775P_cdsp0 = {
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+ .cfgbase = 0x24000000 + 0x180000,
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+ .l2tcm_size = 0x00000000,
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+ .l2vic_base = 0x26300000 + 0x90000,
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+ .l2vic_size = 0x00001000,
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+ .csr_base = 0x26300000,
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+ .qtmr_region = 0x26300000 + 0xA1000,
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+ .cfgtable = {
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+ .l2tcm_base = 0x00002400,
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+ .reserved0 = 0x00000000,
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+ .subsystem_base = 0x00002638,
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+ .etm_base = 0x00002419,
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+ .l2cfg_base = 0x0000241a,
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+ .reserved1 = 0x0000241b,
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+ .l1s0_base = 0x00002500,
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+ .axi2_lowaddr = 0x00000000,
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+ .streamer_base = 0x00000000,
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+ .reserved2 = 0x00000000,
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+ .fastl2vic_base = 0x0000241e,
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+ .jtlb_size_entries = 0x00000080,
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+ .coproc_present = 0x00000001,
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+ .ext_contexts = 0x00000004,
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+ .vtcm_base = 0x00002500,
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+ .vtcm_size_kb = 0x00002000,
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+ .l2tag_size = 0x00000400,
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+ .l2ecomem_size = 0x00000000,
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+ .thread_enable_mask = 0x0000003f,
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+ .eccreg_base = 0x0000241f,
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+ .l2line_size = 0x00000080,
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+ .tiny_core = 0x00000000,
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+ .l2itcm_size = 0x00000000,
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+ .l2itcm_base = 0x00002400,
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+ .reserved3 = 0x00000000,
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+ .dtm_present = 0x00000000,
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+ .dma_version = 0x00000003,
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+ .hvx_vec_log_length = 0x00000007,
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+ .core_id = 0x00000000,
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+ .core_count = 0x00000000,
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+ .coproc2_reg0 = 0x00000040,
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+ .coproc2_reg1 = 0x00000020,
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+ .v2x_mode = 0x00000001,
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+ .coproc2_reg2 = 0x00000008,
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+ .coproc2_reg3 = 0x00000020,
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+ .coproc2_reg4 = 0x00000000,
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+ .coproc2_reg5 = 0x00000002,
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+ .coproc2_reg6 = 0x00000016,
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+ .coproc2_reg7 = 0x00000006,
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+ .acd_preset = 0x00000001,
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+ .mnd_preset = 0x00000000,
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+ .l1d_size_kb = 0x00000010,
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+ .l1i_size_kb = 0x00000020,
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+ .l1d_write_policy = 0x00000002,
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+ .vtcm_bank_width = 0x00000080,
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+ .reserved4 = 0x00000001,
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+ .reserved5 = 0x00000000,
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+ .reserved6 = 0x00000003,
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+ .coproc2_cvt_mpy_size = 0x0000000a,
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+ .consistency_domain = 0x000000e0,
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+ .capacity_domain = 0x00000080,
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+ .axi3_lowaddr = 0x00000000,
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+ },
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+};
hw/hexagon/machine_cfg_v68n_1024.h.inc
new
+64
@@ -0,0 +1,64 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+
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+static const struct hexagon_machine_config v68n_1024 = {
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+ .cfgbase = 0xde000000,
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+ .l2tcm_size = 0x00000000,
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+ .l2vic_base = 0xfc910000,
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+ .l2vic_size = 0x00001000,
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+ .csr_base = 0xfc900000,
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+ .qtmr_region = 0xfc921000,
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+ .cfgtable = {
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+ .l2tcm_base = 0x0000d800,
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+ .reserved0 = 0x00000000,
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+ .subsystem_base = 0x0000fc90,
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+ .etm_base = 0x0000d819,
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+ .l2cfg_base = 0x0000d81a,
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+ .reserved1 = 0x00000000,
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+ .l1s0_base = 0x0000d840,
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+ .axi2_lowaddr = 0x00003000,
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+ .streamer_base = 0x0000d81c,
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+ .reserved2 = 0x0000d81d,
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+ .fastl2vic_base = 0x0000d81e,
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+ .jtlb_size_entries = 0x00000080,
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+ .coproc_present = 0x00000001,
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+ .ext_contexts = 0x00000004,
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+ .vtcm_base = 0x0000d840,
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+ .vtcm_size_kb = 0x00001000,
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+ .l2tag_size = 0x00000400,
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+ .l2ecomem_size = 0x00000400,
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+ .thread_enable_mask = 0x0000003f,
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+ .eccreg_base = 0x0000d81f,
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+ .l2line_size = 0x00000080,
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+ .tiny_core = 0x00000000,
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+ .l2itcm_size = 0x00000000,
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+ .l2itcm_base = 0x0000d820,
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+ .reserved3 = 0x00000000,
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+ .dtm_present = 0x00000000,
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+ .dma_version = 0x00000001,
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+ .hvx_vec_log_length = 0x00000007,
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+ .core_id = 0x00000000,
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+ .core_count = 0x00000000,
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+ .coproc2_reg0 = 0x00000040,
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+ .coproc2_reg1 = 0x00000020,
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+ .v2x_mode = 0x1f1f1f1f,
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+ .coproc2_reg2 = 0x1f1f1f1f,
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+ .coproc2_reg3 = 0x1f1f1f1f,
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+ .coproc2_reg4 = 0x1f1f1f1f,
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+ .coproc2_reg5 = 0x1f1f1f1f,
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+ .coproc2_reg6 = 0x1f1f1f1f,
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+ .coproc2_reg7 = 0x1f1f1f1f,
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+ .acd_preset = 0x1f1f1f1f,
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+ .mnd_preset = 0x1f1f1f1f,
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+ .l1d_size_kb = 0x1f1f1f1f,
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+ .l1i_size_kb = 0x1f1f1f1f,
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+ .l1d_write_policy = 0x1f1f1f1f,
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+ .vtcm_bank_width = 0x1f1f1f1f,
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+ .reserved4 = 0x1f1f1f1f,
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+ .reserved5 = 0x1f1f1f1f,
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+ .reserved6 = 0x1f1f1f1f,
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+ .coproc2_cvt_mpy_size = 0x1f1f1f1f,
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+ .consistency_domain = 0x1f1f1f1f,
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+ .capacity_domain = 0x1f1f1f1f,
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+ .axi3_lowaddr = 0x1f1f1f1f,
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+ },
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+};