target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207
PPC2_LSQ_ISA207 is only ever set in the CPUPPCState's insns_flags2 alongside PPC2_ISA207. Checks made by PPC2_LSQ_ISA207 could be replaced with PPC2_ISA207, hence rendering it useless and apt for removal. This patch does the same. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-33-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Chinmay Rath committed
Aug 27, 2026 at 18:59 UTC
53be3a96b95ac8e97d29c6be8a162f700b21812f
5 files changed
+5
-9
linux-user/ppc/elfload.c
+1
-1
@@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
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do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
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GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
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- GET_FEATURE2((PPC2_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
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+ GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 |
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PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
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QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR));
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GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
target/ppc/cpu.h
-3
@@ -2577,8 +2577,6 @@ enum {
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PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
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/* ISA 2.06B floating point test instructions */
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PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
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- /* ISA 2.07 load/store quadword */
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- PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
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/* ISA 2.07 Altivec */
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PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
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/* PowerISA 2.07 Book3s specification */
@@ -2608,7 +2606,6 @@ enum {
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PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
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PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
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PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
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- PPC2_LSQ_ISA207 | \
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PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
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PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
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PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
target/ppc/cpu_init.c
+1
-2
@@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
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pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
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PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
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- PPC2_FP_TST_ISA206 |
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- PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
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+ PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 |
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PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
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PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
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PPC2_BCDA_ISA206;
target/ppc/cpu_init.h
+1
-1
@@ -18,7 +18,7 @@
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(PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
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PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
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- PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \
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+ PPC2_ALTIVEC_207 | PPC2_ISA205 | \
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PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \
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PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)
24
target/ppc/translate/fixedpoint-impl.c.inc
+2
-2
@@ -124,7 +124,7 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
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REQUIRE_INSNS_FLAGS(ctx, 64BX);
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- if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
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+ if (!prefixed && !(ctx->insns_flags2 & PPC2_ISA207)) {
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/* lq and stq were privileged prior to V. 2.07 */
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REQUIRE_SV(ctx);
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@@ -288,7 +288,7 @@ TRANS64(STDCX, do_store_cond, MO_UQ);
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static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a)
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{
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REQUIRE_64BIT(ctx);
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- REQUIRE_INSNS_FLAGS2(ctx, LSQ_ISA207);
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+ REQUIRE_INSNS_FLAGS2(ctx, ISA207);
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#if defined(TARGET_PPC64)
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TCGLabel *lfail = gen_new_label();
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TCGv ea = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);