target/arm: Implement FCVT (FP16 to FP8) for SME
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
53c3d4906c84c59af30173b86af9093348ebbb02
2 files changed
+18
target/arm/tcg/sme.decode
+2
@@ -863,6 +863,8 @@ BF2CVT 11000001 111 00110 111000 ..... ....0 @zz_2x1
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BF1CVTL 11000001 011 00110 111000 ..... ....1 @zz_2x1
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BF2CVTL 11000001 111 00110 111000 ..... ....1 @zz_2x1
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+FCVT_bh 11000001 001 00100 111000 ....0 ..... @zz_1x2
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+
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ZIP_4 11000001 esz:2 1 10110 111000 ...00 ... 00 \
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&zz_e zd=%zd_ax4 zn=%zn_ax4
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ZIP_4 11000001 001 10111 111000 ...00 ... 00 \
target/arm/tcg/translate-sme.c
+16
@@ -1556,6 +1556,22 @@ TRANS_FEAT(BF2CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 1)
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TRANS_FEAT(BF1CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 0)
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TRANS_FEAT(BF2CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 1)
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+static bool trans_FCVT_bh(DisasContext *s, arg_zz_n *a)
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+{
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+ if (!dc_isar_feature(aa64_sme2_f8cvt, s)) {
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+ return false;
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+ }
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+ if (fpmr_access_check(s) && sme_sm_enabled_check(s)) {
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+ int svl = streaming_vec_reg_size(s);
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+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->zd),
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+ vec_full_reg_offset(s, a->zn),
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+ vec_full_reg_offset(s, a->zn + 1),
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+ tcg_env, svl, svl,
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+ FPST_ZA << 2, gen_helper_gvec_fcvt_bh);
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+ }
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+ return true;
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+}
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+
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static bool do_zipuzp_4(DisasContext *s, arg_zz_e *a,
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gen_helper_gvec_2 * const fn[5])
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{